DESC0024755

In this DOE SBIR topic C57 34.b-1 the DOE Office of Nuclear Physics (NP) seeks new ultra-low-power developments in front-end readout application-specific integrated circuits (ASICs) to amplify and process streaming data from highly-segmented solid-state and gas detectors that generally aid the active-target community to maximize quality of measurements. Alphacore has recently developed, and silicon demonstrated, similar low power readout/digitizer ICs that have multi-channel pre- amplifiers and analog-to-digital converters (ADCs) in low-cost fabrication technology nodes. The proposed intelligent front-end ASIC offers a high-performance digitizer with on-board data processing to more efficiently stream data collection in NP and High Energy Physics (HEP) particle detector experiments as well as high performance imaging systems where no streamed image latency can be tolerated. Alphacoreĺs proposed single chip intelligent front-end ASIC design is optimized for Size, Weight, Power, and Cost (SWaP-C) especially for low-power, low-cost, and rad-hard operation. Alphacore has successfully developed, and silicon demonstrated, similar low power readout ICs with multi-channel pre-amplifiers and ADCs in low-cost fabrication technology nodes. Alphacore recently had detailed detector discussions with Dr. Gerard Visser, from Indiana University, and with Marco Battaglieri, from INFN, who currently work on the EIC EPIC calorimeter readout architecture. They gave Alphacore detailed requirements and a preliminary architecture for the intelligent front-end ASIC that is needed. In Phase I, Alphacore will determine a versatile readout ASIC architecture that optimizes ultra-low-power power consumption and digitization-I/O bandwidth. In Phase I, the feasibility of the intelligent ASIC will be demonstrated by porting Alphacoreĺs silicon-proven HYDRA ADC core to the selected SkyWater 90nm CMOS process (this process provides good transistor performance, excellent inherent radiation hardness, and LOW COST tapeouts), and then designing the 64-channel ASIC using this core. A 16-channel test chip will be fully designed and layout completed so that it can be immediately sent to be fabricated at the beginning of a follow-on Phase II program. Radiation hardness up to EIC levels, i.e., a few megarads will be modeled. Alphacore has been developing low-cost, multi-channel readout ICĺs for NP experiments including Electron-Ion Collider experiments at BNL Relativistic Heavy Ion Collider, the Dark Light Phase I and Phase II experiments at Jefferson Lab, SoLID at JLAB, STAR upgrade at BNL, and planned large nuclear physics experiments at NSCL/FRIB and Texas A&M University. Other detector types of interest include the RICH, mRICH, DIRC light detectors, gas electron multiplier detectors, MICRO MEsh GAseous Structure gaseous parallel plate detectors, Scintillation Detectors integrated with SiPMs, even traditional PMTs (often coupled with scintillators), MCP, Si strip detectors, and Calorimeters.