High-channel count, picosecond timing resolution and extreme radiation hardness time to digital converter.
Grant Program (CFDA)
Place of Performance
Dayton, Ohio 45431-3833 United States
Single Zip Code
Prixarc was awarded Project Grant DESC0022794 worth $199,899 from the Office of Science in June 2022 with work to be completed primarily in Dayton Ohio United States. The grant has a duration of 9 months and was awarded through assistance program 81.049 Office of Science Financial Assistance Program. The Project Grant was awarded through grant opportunity FY 2022 SBIR/STTR Phase I Release 2.
SBIR Phase I
High-Channel Count, Picosecond Timing Resolution and Extreme Radiation Hardness Time to Digital Converter
Prixarc will partner with Alphacore Inc. to develop and commercialize high-precision, high-resolution, and high-channel count timing measurement systems for next generation detectors in high energy nuclear physics experiments. We will develop a custom Application Specific Integrated Circuit (ASIC)-based 64-channel Time to Digital Converter (TDC) with RMS time precision better than 10 ps, operational temperature range from 77 K to 300 K, and radiation hardness to 100 Mrad (Si) using Skywater Technology RH90nm FDSOI CMOS process. General statement of how this problem is being addressed. The proposed TDC with high time precision, high radiation hardness, and high channel count is possible because of two novel aspects: (i) stochastic TDC design [Radiation Hardened by Design (RHBD)] and (ii) a fully depleted silicon-on-insulator (FDSOI) complementary metal–oxide–semiconductor (CMOS) fabrication process [Radiation Hardened by Process (RHBP)]. What is to be done in Phase I? During Phase I, we will study ASIC design and fabrication considerations for extreme radiation and low-temperature operational environments. We will device a stochastic TDC architecture with self-calibration. We will develop transition plan/business case analysis. We will identify technological and reliability challenges of our design approach and propose viable risk mitigation strategies. The circuit design and simulation results will be our key deliverable. Following Phase I, the most promising TDC design will be further refined, fabricated, and tested in Phase II and offered as an integrated hardware module. Commercial Applications and Other Benefits (limited to the space provided). The TDC will play an increasingly important role in the nano-CMOS era, because it is well suited to implementation with nanoscale digital CMOS processes. The proposed high-performance TDC and processor is useful for a variety of applications in spacecrafts, satellites, communications, medical imaging, electronic warfare, and photonic integrated circuits. The success of this project will lead to high performance TDC systems that can be applied to both consumer/industrial applications and specialized radiation environments for nuclear physics applications. In addition, the proposed work would utilize new domestic U.S. based CMOS process for development and manufacturing of next generation radiation hardened and cryogenic integrated circuits.
Last Modified 7/18/22
Period of Performance
100.0% Federal Funding
0.0% Non-Federal Funding
Award ID FAIN
Award ID URI
892430 SC CHICAGO SERVICE CENTER
J.D. (James) Vance
J.D. (James) Vance
|Science, Energy Programs, Energy (089-0222)
|General science and basic research
|Grants, subsidies, and contributions (41.0)