2414353
Project Grant
Overview
Grant Description
SbIR Phase I: Enhanced parallelism for faster simulation and validation of integrated circuits.
The broader impact/commercial impacts of this Small Business Innovation Research (SBIR) Phase I project will be in significant reduction of the time required to design complex integrated circuits (ICs) and accomplish comprehensive verification.
ICs are integral part of modern electronic devices and play a critical role in determining device performance and cost.
However, exponentially rising demand for better smartphones, tablets, laptops, etc., is forcing IC designers to include more features within a smaller format.
These complex designs can take months for complete verification using the current state-of-the-art tools (simulators and emulators).
Due to extremely high market competition, IC manufacturers are doing partial design verification and launching the products in the market.
This is causing increased revocation of launched products, consumer dissatisfaction, loss of billions of dollars, and generation of e-waste.
This work will enable comprehensive verification of ICs at a faster rate and lower cost thereby preventing massive economic losses and environmental pollution.
This Small Business Innovation Research (SBIR) Phase I project aims to develop a technology that will provide IC design houses a distinctive advantage over the competition concerning time-to-market, risk, and remediation of post-silicon bugs, and design NRE (non-recurring engineering) by dramatically improving simulation performance.
The innovation is based on successfully minimizing the limitations imposed by Amdahl’s Law.
To overcome Amdahl’s Law, the company is developing an instruction-less, configurable computer architecture.
It incorporates a bulk synchronous data flow architecture, using a proprietary data format and algorithm.
The technology can in effect turn a single FPGA (field-programmable gate array) into hundreds of incredibly fast virtual processors that can concurrently solve product terms for equations at the speed of the processor-to-memory interface.
The company has developed an initial virtual processor called the Boolean Processing Unit (BPU).
The software converts the design from Verilog into a set of sum-of-product form Boolean equations, that the BPU can solve via targeting IC behavioral simulation computing, 30x faster than existing simulators.
The innovation has the potential to provide emulator performance at simulator cost and features.
This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the foundation's intellectual merit and broader impacts review criteria.
Subawards are not planned for this award.
The broader impact/commercial impacts of this Small Business Innovation Research (SBIR) Phase I project will be in significant reduction of the time required to design complex integrated circuits (ICs) and accomplish comprehensive verification.
ICs are integral part of modern electronic devices and play a critical role in determining device performance and cost.
However, exponentially rising demand for better smartphones, tablets, laptops, etc., is forcing IC designers to include more features within a smaller format.
These complex designs can take months for complete verification using the current state-of-the-art tools (simulators and emulators).
Due to extremely high market competition, IC manufacturers are doing partial design verification and launching the products in the market.
This is causing increased revocation of launched products, consumer dissatisfaction, loss of billions of dollars, and generation of e-waste.
This work will enable comprehensive verification of ICs at a faster rate and lower cost thereby preventing massive economic losses and environmental pollution.
This Small Business Innovation Research (SBIR) Phase I project aims to develop a technology that will provide IC design houses a distinctive advantage over the competition concerning time-to-market, risk, and remediation of post-silicon bugs, and design NRE (non-recurring engineering) by dramatically improving simulation performance.
The innovation is based on successfully minimizing the limitations imposed by Amdahl’s Law.
To overcome Amdahl’s Law, the company is developing an instruction-less, configurable computer architecture.
It incorporates a bulk synchronous data flow architecture, using a proprietary data format and algorithm.
The technology can in effect turn a single FPGA (field-programmable gate array) into hundreds of incredibly fast virtual processors that can concurrently solve product terms for equations at the speed of the processor-to-memory interface.
The company has developed an initial virtual processor called the Boolean Processing Unit (BPU).
The software converts the design from Verilog into a set of sum-of-product form Boolean equations, that the BPU can solve via targeting IC behavioral simulation computing, 30x faster than existing simulators.
The innovation has the potential to provide emulator performance at simulator cost and features.
This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the foundation's intellectual merit and broader impacts review criteria.
Subawards are not planned for this award.
Awardee
Funding Goals
THE GOAL OF THIS FUNDING OPPORTUNITY, "NSF SMALL BUSINESS INNOVATION RESEARCH (SBIR)/ SMALL BUSINESS TECHNOLOGY TRANSFER (STTR) PROGRAMS PHASE I", IS IDENTIFIED IN THE LINK: HTTPS://WWW.NSF.GOV/PUBLICATIONS/PUB_SUMM.JSP?ODS_KEY=NSF23515
Grant Program (CFDA)
Awarding / Funding Agency
Place of Performance
Woodinville,
Washington
98077-6732
United States
Geographic Scope
Single Zip Code
Grayskytech was awarded
Project Grant 2414353
worth $275,000
from National Science Foundation in October 2024 with work to be completed primarily in Woodinville Washington United States.
The grant
has a duration of 8 months and
was awarded through assistance program 47.084 NSF Technology, Innovation, and Partnerships.
The Project Grant was awarded through grant opportunity NSF Small Business Innovation Research / Small Business Technology Transfer Phase I Programs.
SBIR Details
Research Type
SBIR Phase I
Title
SBIR Phase I: Enhanced Parallelism for Faster Simulation and Validation of Integrated Circuits
Abstract
The broader impact/commercial impacts of this Small Business Innovation Research (SBIR) Phase I project will be in significant reduction of the time required to design complex integrated circuits (ICs) and accomplish comprehensive verification. ICs are integral part of modern electronic devices and play a critical role in determining device performance and cost. However, exponentially rising demand for better smartphones, tablets, laptops, etc., is forcing IC designers to include more features within a smaller format. These complex designs can take months for complete verification using the current state-of-the-art tools (simulators and emulators). Due to extremely high market competition, IC manufacturers are doing partial design verification and launching the products in the market. This is causing increased revocation of launched products, consumer dissatisfaction, loss of billions of dollars, and generation of e-waste. This work will enable comprehensive verification of ICs at a faster rate and lower cost thereby preventing massive economic losses and environmental pollution.
This Small Business Innovation Research (SBIR) Phase I project aims to develop a technology that will provide IC design houses a distinctive advantage over the competition concerning time-to-market, risk, and remediation of post-silicon bugs, and design NRE (non-recurring engineering) by dramatically improving simulation performance. The innovation is based on successfully minimizing the limitations imposed by Amdahl’s law. To overcome Amdahl’s law, the company is developing an instruction-less, configurable computer architecture. It incorporates a bulk synchronous data flow architecture, using a proprietary data format and algorithm. The technology can in effect turn a single FPGA (field-programmable gate array) into hundreds of incredibly fast virtual processors that can concurrently solve product terms for equations at the speed of the processor-to-memory interface. The company has developed an initial virtual processor called the Boolean Processing Unit (BPU). The software converts the design from Verilog into a set of Sum-of-Product form Boolean equations, that the BPU can solve via targeting IC behavioral simulation computing, 30x faster than existing simulators. The innovation has the potential to provide emulator performance at simulator cost and features.
This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.
Topic Code
S
Solicitation Number
NSF 23-515
Status
(Complete)
Last Modified 10/8/24
Period of Performance
10/1/24
Start Date
6/30/25
End Date
Funding Split
$275.0K
Federal Obligation
$0.0
Non-Federal Obligation
$275.0K
Total Obligated
Activity Timeline
Additional Detail
Award ID FAIN
2414353
SAI Number
None
Award ID URI
SAI EXEMPT
Awardee Classifications
Small Business
Awarding Office
491503 TRANSLATIONAL IMPACTS
Funding Office
491503 TRANSLATIONAL IMPACTS
Awardee UEI
YQ52VVZ5UMM8
Awardee CAGE
9BNF6
Performance District
WA-08
Senators
Maria Cantwell
Patty Murray
Patty Murray
Modified: 10/8/24