2304304
Project Grant
Overview
Grant Description
Sbir Phase I: A Mixed-Computation Neural Network Acceleration Stack for Edge Inference -The broader/commercial impact of this Small Business Innovation Research (SBIR) Phase I project is to improve the sustainability of artificial intelligence by reducing carbon emissions for training neural networks and performing inference at the edge. Additionally, the technology will spawn new applications and use cases for edge inference (including personal health, advanced data analytics, and informed decision-making), resulting in significant improvements in people's lives and well-being.
The commercial potential is substantial (i.e., tens of billions of dollars annually), as are the potential economic benefits to US high-technology industries. This Small Business Innovation Research (SBIR) Phase I project sets out to develop a mixed-computation neural network acceleration stack utilizing optimally designed and provisioned hardware resources. This acceleration stack empowers a heterogeneous hardware realization of a neural network inference engine whereby computations required in various network layers may be done by using different number systems and different precision levels.
The acceleration stack can thus achieve very high inference speed and energy efficiency while maintaining the inference accuracy compared to a homogeneous hardware realization of the network using 16-bit floating point computations. To support the design, optimization, and runtime efficiency of this edge inference accelerator, a full suite of software and design automation tools comprising a distiller for neural network architecture optimization and training, a logic synthesizer for generating optimized gate-level realization of very large and complex Boolean and multi-valued logic functions, a compiler for generating and scheduling control-flow and data path instructions that are executed on the target fabric, and a runtime system for orchestrating data movement will also be provided.
The resulting edge inference accelerator will be deployable on resource-constrained, energy-limited, and cost-sensitive edge devices. This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria. - Subawards are not planned for this award.
The commercial potential is substantial (i.e., tens of billions of dollars annually), as are the potential economic benefits to US high-technology industries. This Small Business Innovation Research (SBIR) Phase I project sets out to develop a mixed-computation neural network acceleration stack utilizing optimally designed and provisioned hardware resources. This acceleration stack empowers a heterogeneous hardware realization of a neural network inference engine whereby computations required in various network layers may be done by using different number systems and different precision levels.
The acceleration stack can thus achieve very high inference speed and energy efficiency while maintaining the inference accuracy compared to a homogeneous hardware realization of the network using 16-bit floating point computations. To support the design, optimization, and runtime efficiency of this edge inference accelerator, a full suite of software and design automation tools comprising a distiller for neural network architecture optimization and training, a logic synthesizer for generating optimized gate-level realization of very large and complex Boolean and multi-valued logic functions, a compiler for generating and scheduling control-flow and data path instructions that are executed on the target fabric, and a runtime system for orchestrating data movement will also be provided.
The resulting edge inference accelerator will be deployable on resource-constrained, energy-limited, and cost-sensitive edge devices. This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria. - Subawards are not planned for this award.
Awardee
Funding Goals
THE GOAL OF THIS FUNDING OPPORTUNITY, "NSF SMALL BUSINESS INNOVATION RESEARCH (SBIR)/ SMALL BUSINESS TECHNOLOGY TRANSFER (STTR) PROGRAMS PHASE I", IS IDENTIFIED IN THE LINK: HTTPS://WWW.NSF.GOV/PUBLICATIONS/PUB_SUMM.JSP?ODS_KEY=NSF22551
Grant Program (CFDA)
Awarding / Funding Agency
Place of Performance
Marina Del Rey,
California
90292-6606
United States
Geographic Scope
Single Zip Code
Related Opportunity
22-551
Nouvai was awarded
Project Grant 2304304
worth $274,915
from National Science Foundation in December 2023 with work to be completed primarily in Marina Del Rey California United States.
The grant
has a duration of 8 months and
was awarded through assistance program 47.084 NSF Technology, Innovation, and Partnerships.
SBIR Details
Research Type
SBIR Phase I
Title
SBIR Phase I: A Mixed-Computation Neural Network Acceleration Stack for Edge Inference
Abstract
The broader/commercial impact of this Small Business Innovation Research (SBIR) Phase I project is to improve the sustainability of artificial intelligence by reducing carbon emissions for training neural networks and performing inference at the edge. Additionally, the technology will spawn new applications and use cases for edge inference (including personal health, advanced data analytics, and informed decision-making), resulting in significant improvements in people's lives and well-being. The commercial potential is substantial (i.e., tens of billions of dollars annually), as are the potential economic benefits to US high-technology industries.
This Small Business Innovation Research (SBIR) Phase I project sets out to develop a mixed-computation neural network acceleration stack utilizing optimally designed and provisioned hardware resources. This acceleration stack empowers a heterogeneous hardware realization of a neural network inference engine whereby computations required in various network layers may be done by using different number systems and different precision levels. The acceleration stack can thus achieve very high inference speed and energy efficiency while maintaining the inference accuracy compared to a homogeneous hardware realization of the network using 16-bit floating point computations. To support the design, optimization, and runtime efficiency of this edge inference accelerator, a full suite of software and design automation tools comprising a distiller for neural network architecture optimization and training, a logic synthesizer for generating optimized gate-level realization of very large and complex Boolean and multi-valued logic functions, a compiler for generating and scheduling control-flow and data path instructions that are executed on the target fabric, and a runtime system for orchestrating data movement will also be provided. The resulting edge inference accelerator will be deployable on resource-constrained, energy-limited, and cost-sensitive edge devices.
This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.
Topic Code
AI
Solicitation Number
NSF 22-551
Status
(Complete)
Last Modified 12/21/23
Period of Performance
12/15/23
Start Date
8/31/24
End Date
Funding Split
$274.9K
Federal Obligation
$0.0
Non-Federal Obligation
$274.9K
Total Obligated
Activity Timeline
Additional Detail
Award ID FAIN
2304304
SAI Number
None
Award ID URI
SAI EXEMPT
Awardee Classifications
Small Business
Awarding Office
491503 TRANSLATIONAL IMPACTS
Funding Office
491503 TRANSLATIONAL IMPACTS
Awardee UEI
QNDYZ7NR49S4
Awardee CAGE
9KDB2
Performance District
CA-36
Senators
Dianne Feinstein
Alejandro Padilla
Alejandro Padilla
Modified: 12/21/23