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2304119

Project Grant

Overview

Grant Description
SBIR Phase I: Liquid-Enabled Advanced Pitch (LEAP) Semiconductor Manufacturing - The broader/commercial impact of this Small Business Innovation Research (SBIR) Phase I project is the development of materials and processes for semiconductor manufacturing that will enable the progression of Moore's Law and help to strengthen domestic semiconductor manufacturing capacity and capability.

Recent supply chain issues have plagued the semiconductor industry, and this has had ripple effects throughout the American economy. The majority of advanced semiconductor manufacturing capacity is outside of the U.S., and this recent shortage has highlighted the need for domestic foundries both for economic vitality in the U.S. as well as national security and supply chain resiliency.

In 2019, American semiconductor foundries directly employed 184,600 workers, down from 292,100 (-37%) in 2001. The main loss of manufacturing jobs was attributed to the utilization of offshore foundries. Currently, U.S. semiconductor manufacturing represents just 1% of global capacity, and 80% of U.S. semiconductor manufacturing capacity is in the 200 mm (8-inch) format, which is not compatible with the most advanced, high-performance processes, limiting production to >65 nm nodes.

This project will increase the competitiveness of currently established U.S.-based foundries as well as increase the performance of foundries that are under construction. This project seeks to develop and validate the performance of several required materials to enable the integration of a novel semiconductor manufacturing process that has the capability to double the density of features in current cutting-edge semiconductor chip manufacturing processes. This solution may also simplify the overall manufacturing process, without the need for intensive capital expenditures.

At the conclusion of this project, the performance of the developed materials and the resulting manufacturing improvement will be demonstrated on both 8-inch and 12-inch formats. The process begins with conventional photolithography on a chemically amplified resist to define a relief pattern. A trencher material is then coated on top of and diffused into the pattern, creating a self-aligned layer of polarity-switched material at the sidewalls of the resist. A masker is then applied to fill the openings in the pattern, and the final pitch-doubled pattern is revealed. The diffusion-controlled process achieves a similar result to alternative processes without the need for expensive tool upgrades. The technology can extend canonical lithography methods by up to 2 nodes, reduce production costs by more than 80%, and reduce patterning errors to improve yield. Importantly, the process is applicable to 8-inch wafers, bringing advanced node dimensionality to older fabs.

This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.
Awardee
Awarding / Funding Agency
Place of Performance
Northport, New York 11768-1338 United States
Geographic Scope
Single Zip Code
Related Opportunity
None
Geminatio was awarded Project Grant 2304119 worth $275,000 from National Science Foundation in July 2023 with work to be completed primarily in Northport New York United States. The grant has a duration of 1 year and was awarded through assistance program 47.084 NSF Technology, Innovation, and Partnerships.

SBIR Details

Research Type
SBIR Phase I
Title
SBIR Phase I:Liquid-Enabled Advanced Pitch (LEAP) Semiconductor Manufacturing
Abstract
The broader/commercial impact of this Small Business Innovation Research (SBIR) Phase I project is the development of materials and processes for semiconductor manufacturing that will enable the progression of Moore’s Law and help to strengthen domestic semiconductor manufacturing capacity and capability. Recent supply chain issues have plagued the semiconductor industry, and this has had ripple effects throughout the American economy. The majority of advanced semiconductor manufacturing capacity is outside of the U.S. and this recent shortage has highlighted the need for domestic foundries both for economic vitality in the U.S. as well as national security and supply chain resiliency. In 2019, American semiconductor foundries directly employed 184,600 workers, down from 292,100 (-37%) in 2001. The main loss of manufacturing jobs was attributed to the utilization of offshore foundries.Currently, U.S. semiconductor manufacturing represents just 1% of global capacity and 80% of U.S. semiconductor manufacturing capacity is in the 200 mm (8-inch) format, which is not compatible with the most advanced, high-performance processes, limiting production to greater than65 nm nodes. This project will increase the competitiveness of currently established U.S.-based foundries as well as increase the performance of foundries that are under construction. _x000D_ _x000D_ This project seeks to develop and validate the performance of several required materials to enable the integration of a novel semiconductor manufacturing process that has the capability to double the density of features in current cutting-edge semiconductor chip manufacturing processes.This solution may also simplify the overall manufacturing process, without the need for intensive capital expenditures. At the conclusion of this project, the performance of the developed materials and the resulting manufacturing improvement will be demonstrated on both 8-inch and 12-inch formats. The process begins with conventional photolithography on a chemically amplified resist to define a relief pattern. A Trencher material is then coated on top of and diffused into the pattern, creating a self-aligned layer of polarity-switched material at the sidewalls of the resist. A Masker is then applied to fill the openings in the pattern, and the final pitch-doubled pattern is revealed. The diffusion-controlled process achieves a similar result to alternative processes without the need for expensive tool upgrades.The technology can extend canonical lithography methods by up to 2 nodes, reduce production costs by more than 80%, and reduce patterning errors to improve yield. Importantly, the process is applicable to 8-inch wafers, bringing advanced node dimensionality to older fabs._x000D_ _x000D_ This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.
Topic Code
S
Solicitation Number
NSF 22-551

Status
(Complete)

Last Modified 8/3/23

Period of Performance
7/15/23
Start Date
6/30/24
End Date
100% Complete

Funding Split
$275.0K
Federal Obligation
$0.0
Non-Federal Obligation
$275.0K
Total Obligated
100.0% Federal Funding
0.0% Non-Federal Funding

Activity Timeline

Interactive chart of timeline of amendments to 2304119

Additional Detail

Award ID FAIN
2304119
SAI Number
None
Award ID URI
SAI EXEMPT
Awardee Classifications
Small Business
Awarding Office
491503 TRANSLATIONAL IMPACTS
Funding Office
491503 TRANSLATIONAL IMPACTS
Awardee UEI
FK9FELDSRK63
Awardee CAGE
None
Performance District
NY-01
Senators
Kirsten Gillibrand
Charles Schumer

Budget Funding

Federal Account Budget Subfunction Object Class Total Percentage
Research and Related Activities, National Science Foundation (049-0100) General science and basic research Grants, subsidies, and contributions (41.0) $275,000 100%
Modified: 8/3/23