N6426724C0080

Small Business Innovation Research Program (SBIR) Phase II

Radiation Hardened Time Triggered Ethernet IP

Development of a Time-Triggered Ethernet Intellectual Property Block

As a response to Navy s Navy SBIR Topic N221-080, Alphacore will develop a radiation hardened Time-Triggered Ethernet (TTEthernet) Intellectual Property (IP) block for hard real-time control applications in next-generation avionics architectures. This proposed work will integrate Alphacore s advanced radiation hardened physical layer (PHY chip) with network level radiation hardened TTEthernet protocol implementation. The proposed system will be designed to be implemented on GlobalFoundries 22nm Fully-Depleted Silicon-on-Insulator (FD-SOI) fabrication platform called GF22FDX. A GF22FDX test chip will be fabricated, tested, and demonstrated by the end of Phase II. Based on discussions with GlobalFoundries, the GF22FDX process will be available on-shore in 2024, before our tapeout date. There is also a plan to have a radiation-hard GF22FDX variant called GF22FDX-RH available and on-shore towards the end of this program. Objectives for the proposed Phase II are: Objective 1) Optimize TTEthernet IP for ASIC implementation. Objective 2) Complete a selected set of radiation hard standard cells in GF22FDX. Objective 3) Optimize PHY. Objective 4) Integrate TTE IP and PHY on an ASIC test chip and send it to fabrication. Objective 5) Package and test. Objective 6) Radiation Test the fabricated test chips.

The goal of phase II is to continue the R&D efforts initiated in Phase I. Funding is based on the results achieved in Phase I and the scientific and technical merit and commercial potential of the project proposed in Phase II.

N221-080

N221-080-1152

22.1

Austin H Roach