Synthesizable Register Transfer Logic (RTL) Assertions

OUSD (R&E) MODERNIZATION PRIORITY: Microelectronics TECHNOLOGY AREA(S): Electronics OBJECTIVE: Develop a library of practical synthesizable register transfer logic (RTL) assertions (System Verilog is highly preferred), investigate limitations of synthesizable assertions in both integrated circuit (IC) and field programmable gate array (FPGA) design and design verification flows using already existing EDA platforms, and develop a methodology for synthesizable RTL assertions and error reporting. Identify robust test vehicles and implement synthesizable RTL assertions in both an FPGA and an IC. DESCRIPTION: In the design verification (DV) of digital circuit design, it is very common for the RTL coder to include assertions in their RTL code, commonly known as assertion-based verification (ABV). These assertions are non-synthesizable as their purpose is solely for design verification, and add nothing to the mission mode of the RTL. They are used in the design verification process to monitor that correct signals, timing and sequences are being maintained. However, for hardware assurance, it may be desirable in the mission mode to have additional circuitry that monitors that correct signals, synchronous timing and sequences are being maintained. Some prior research has been done and involve the creation of a novel synthesis compiler [1], or requiring the use of high level synthesis (HLS) compilers [2]. However, most digital designers will not have access to customer compilers or HLS compilers. And some prior research has been done [3-5] but not fully realized with practical digital design and digital design verification (DV) best practices for FPGA and digital IC development. PHASE I: Perform a feasibility study that defines a commonly used IC electronic design application (EDA) platform, and a commonly used FPGA design platform for the investigation. The investigation will not involve creating a new synthesis tool or compiler, but to use industry standard EDA tools. Investigate and develop appropriate test vehicles, either organic or procured. Many practical assertions involve comparing signals at different RTL hierarchy modules. But for more efficient area, many times hierarchies are flattened during synthesis. Also, it would be desirable to be to have some assertions to be synthesized and some not. Investigate the practicality and any limitations of synthesizable RTL assertion code (System Verilog is highly preferred, research has already been done on synthesizable ANSI-C assertions [2]) in both IC and FPGA platforms regarding best practices in digital design and digital DV including (but not limited to): lint, clock domain crossing (CDC), reset domain crossing (RDC), synthesis design constraints (SDC), signal hierarchy, synthesis, scan chain insertion, area, logic equivalence check (LEC) and code coverage. Additionally, propose a practical methodology for how synthesizable assertions and error reporting are integrated into the digital design flow for both IC and FPGA development. PHASE II: Phase II will result in building, testing and delivering a fully functional prototype or technology of the method developed in phase I. Identify robust test vehicles. Review lint, clock domain crossing (CDC) and reset domain crossing (RDC) reports. Review synthesis design constraints (SDC) file. Perform thorough design verification (DV) including (but not limited to): a functional verification matrix (FVM), a means of monitoring the progress and completion of the FVM, unified top-level test bench, definition of constrained random variables (CRV's), proper regression runs based on the state space of the CRV's, and code coverage reports. RTL code should have assertions, with some assertions monitoring signals at different levels of code hierarchy. Assertions need to be tested against false positives and false negatives. For the IC platform, review synthesis scripts. Perform synthesis with no assertions synthesized, and some chosen assertions synthesized in both IC and FPGA platforms with the hierarchy flattened. For the IC platform, insert a scan chain and enable clock gating during synthesis. For the FPGA platform, continue through implementation phase (with and without synthesized assertions), and prove functionality of the FPGA. For the IC platform, review place and route scripts, review place and route reports, static timing analysis reports, LEC reports and perform automated test pattern generation (ATPG). Actual manufacturing of the IC would be ideal, but may not be practical. PHASE III DUAL USE APPLICATIONS: Phase III will result in error monitoring that would be useful in commercial applications as part of built-in self-test BIST, having potential benefits of improved performance robustness and test time savings. During a Phase III program, offerors may refine the performance of the design and produce pre-production quantities for evaluation by the Government. REFERENCES: Y. Oddos, et al, From Assertion-based Verification to Assertion-based Synthesis , 17th International Conference on Very Large Scale Integration, Oct 2009. Mohamed Hammouda, et al, A Design Approach to Automatically Synthesize ANSI-C Assertion During High-Level Synthesis of Hardware Accelerators 2014 IEEE International Symposium on Circuits and Systems, June 2014. Ivan Kastelan, Zoran Krajacevic, Synthesizable SystemVerilog Assertions as a Methodology for SoC Verification , First IEEE Eastern European Conference of Computer Based Systems, 2009. Sayantan Das, et al, Synthesis of System Verilog Assertions EDAA, 2006. Omar Amin, et al, System Verilog Assertions Synthesis Based Compiller 17th International Workshop on Microprocessors and SOC Test and Verification , 2016. KEYWORDS: FPGA; Digital ASIC; Design Verification; Hardware Assurance