Scaled Silicon Carbide on Insulator for Quantum Applications

TECHNOLOGY AREAS: Sensors; Materials; Information Systems The technology within this topic is restricted under the International Traffic in Arms Regulation (ITAR), 22 CFR Parts 120-130, which controls the export and import of defense-related material and services, including export of sensitive technical data, or the Export Administration Regulation (EAR), 15 CFR Parts 730-774, which controls dual use items. Offerors must disclose any proposed use of foreign nationals (FNs), their country(ies) of origin, the type of visa or work permit possessed, and the statement of work (SOW) tasks intended for accomplishment by the FN(s) in accordance with section 3.5 of the Announcement. Offerors are advised foreign nationals proposed to perform on this topic may be restricted due to the technical data under US Export Control Laws. OBJECTIVE: The Air Force is interested in wafer-scale, quantum-grade silicon carbide on insulator (SiC-OI) as a product to develop next generation integrated quantum photonics technologies. Minimum requirements should be at least 100 millimeter wafers, sub-micron device layer thickness, and total thickness variation below 20 nanometers. DESCRIPTION: There are existing processes used to produce few millimeter scale, but these need to be scaled up and developed at the wafer scale in order to support high volume production. To-date, epitaxial growth of isotopically pure silicon carbide (SiC) on top of a commercial SiC wafer substrate, followed by bonding onto an SiO2 handle wafer, followed by a CMP etch to get to a ~200 nanometer thickness of the epitaxially grown SiC layer has produced material quality sufficient for quantum applications at the few mm scale. Thickness uniformity of this process suffers at larger scales and this work would involve process development and control to scale to the larger wafer-scale. PHASE I: This topic is intended for technology proven ready to move directly into a Phase II. Therefore, a Phase I award is not required. The offeror is required to provide detail and documentation in the Direct to Phase II proposal which demonstrates accomplishment of a Phase I-like effort, including a feasibility study. This includes determining, insofar as possible, the scientific and technical merit and feasibility of ideas appearing to have commercial potential, demonstrating the ability to produce few millimeter scale materials suitable for quantum applications, and possession of the tools and equipment necessary to produce materials at the wafer-scale. The offeror must show they possess the necessary equipment such as wafer bonders, CMP machines, isotopic purification of SiC, and epitaxial growth equipment necessary to produce materials at the wafer scale. It must have validated the product-market fit between the proposed solution and a potential AF stakeholders. PHASE II: Eligibility for D2P2 is predicated on the offeror having performed a Phase I-like effort predominantly separate from the SBIR Programs. Under the phase II effort, the offeror shall develop minimum 100 mm SiC-OI wafers with total thickness variation (TTV) less than 20 nanometers, surface roughness less than 0.5 nanometers, isotopically purified SiC device layers of less than 1 micrometer thickness, and demonstrated optical losses in the device layer of less than 1 decibels/centimeter. The offeror shall also demonstrate a commercially viable process yield for meeting the above wafer metrics. Identification of manufacturing/production issues and or business model modifications required to further improve product or process relevance to improved sustainment costs, availability, or safety, should be documented. These Phase II awards are intended to provide a path to commercialization, not the final step for the proposed solution. PHASE III DUAL USE APPLICATIONS: The contractor will pursue commercialization of the various technologies developed in Phase II for transitioning expanded mission capability to a broad range of potential government and civilian users and alternate mission applications. Direct access with end users and government customers will be provided with opportunities to receive Phase III awards for providing the government additional research & development, or direct procurement of products and services developed in coordination with the program. Potential follow-on Phase III efforts would include fabrication and processing of integrated quantum photonics optical components and testing of components, deterministic spin defect and color center placement/implantation, and process development for electrical biasing. REFERENCES: 1. https://login.wrs.idm.oclc.org/login?qurl KEYWORDS: integrated quantum photonics; silicon carbide; color centers; integrated photonics; spin defects;