Radiation Hardened Cache Memory

OBJECTIVE: Develop a power efficient, high speed, radiation hardened memory device suitable for long term space missions by using carbon nanotubes (CNT) or other innovative materials and processes, (e.g.graphene), processes (3-D), & architectures (memristive). DESCRIPTION: In order to meet projected growth in broadband military satellite communications, future generations of payloads will be required to process the waveform at a significantly higher rate. Unacceptably long memory cycle times can diminish the performance of payload front-end processing by adding undesirable time lags and leading to poor overall payload performance. To address this concern, the Air Force seeks a new generation of radiation hardened cache memory devices capable of allowing the central processing unit (CPU) to operate with minimum memory cycle time by avoiding the introduction of wait states. Before the next generation cache memory is viable for insertion into a space mission, the materials and/or fabrication process must be proven reliable, affordable, and of a density and performance that makes the memory component attractive as an alternative to the current generation of space memory. In particular, the cache memory device must be shown capable of meeting the timing constraints of an emerging generation of space qualified general purpose and special purpose processors, while withstanding the full range of natural and manmade threats encountered in a long term, geosynchronous space environment. The purpose of this topic is to support research into innovative materials and/or processes leading to a high speed cache memory device. In order to better cope with the complex radiation environments, spacecraft electronics are often implemented in a"radiation-hardened"form that is three or more generations behind the contemporary commercial state-of-the-art. Since spacecraft are furthermore power-constrained, the effects of these performance penalties are compounded by an inability to field enough of the slower components to mitigate this gap. Component selections are limited, especially for specialty memories, which stand-alone cache (e.g.,"level 2"or"L2") are considered to be. Despite the compelling benefits that effective cache architectures can provide to general- purpose computation, much less attention is paid in developing these options as in developing the processor or FPGA components that might take advantage of them. In this topic, we seek creative innovations that will give us better options for larger, lower-power, and higher-performance (measured in reduced average access delays from processors) memory components that can either augment a traditional memory hierarchy or effectively collapse it (for example, by having a L2 cache large enough to fit most problems of interest without having cache miss events). The answer need not be confined to a traditional component solution, but can involve new interpretations of hybrid memory, stacked components (for example, using through-silicon vias), even possibly three-dimensional architectures that more effectively collocate processing resources with larger, more efficient memory structures. It may be advantageous to examine new architectural approaches, such as memristors, and materials, such as carbon nanotubes, phase-change materials, or grapheme. Along with these notions of better memory technologies, we must overlay the considerable constraints of working in space. Before the next-generation cache memory is viable for insertion into a space mission, the materials and/or fabrication process must be proven reliable, affordable, and of a density and performance that makes the memory component attractive as an alternative to the current generation of space memory. In particular, the cache memory device must be shown capable of meeting the timing constraints of an emerging generation of space-qualified general purpose and special purpose processors, while withstanding the full range of natural and manmade threats encountered in a long-term, geosynchronous space environment. And of course, the cost of modern microelectronics fabrication provides a challenge as great as most of the other technical barriers. Example goals include access time>16 Mbits, simple voltage supply (e.g.,