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Radiation Hard CMOS Sensors and Engineered Substrates for Detectors at High Energy Colliders

ID: 36a • Type: SBIR / STTR Topic • Match:  90%
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Description

a. Radiation Hard CMOS Sensors and Engineered Substrates for Detectors at High Energy Colliders Silicon detectors for high energy physics are currently based on hybrid technology, with separately fabricated diode strip or pixel sensors and bump-bonded Complementary Metal Oxide Semiconductor (CMOS) readout chips. As larger area detectors are required for tracking and also for new applications such as high granularity calorimetry, lower manufacturing cost is needed. For use in high energy physics, detectors must withstand both ionizing and displacement damage radiation, and they must have fast signal collection and fast readout as well as radiation tolerance in the range 100 to 1000 Mrad and 1E14 to 2E16 neutron equivalent fluence. Of interest are monolithic CMOS-based sensors with moderate depth (5-20 micron) high resistivity substrates that can be fully depleted and can achieve charge collection times of 20 ns or less. Technologies of interest include deep n- and p-wells to avoid parasitic charge collection in CMOS circuitry and geometries with low capacitance charge collection nodes. We aim for stitched, large area arrays of sensors with sensor thickness less than 50 microns and pixel pitch of less than 25 microns. Also of interest are low to moderate gain (x10-50) reach-through silicon avalanche diodes (LGADs) as a proposed sensor type to achieve ~10 ps time resolution for collider experiments. The current generation of reach-through diodes suffers from large fractional dead area at the edges of the pixel and only moderate radiation hardness. A moderately doped thin buried (~5 micron) layer replacing a reach-through implant can address some of these problems. We seek substrate fabrication technologies to improve the radiation hardness and stability of these devices by using graded epitaxy or wafer bonding to produce a buried and moderately doped (1E16) thin buried gain layer on a high resistivity substrate. We also seek techniques to arrange internal doping of detectors by multiple thick epitaxial layers or other methods to allow engineering of the internal fields and resulting pulse shape. Questions Contact: Helmut Marsiske, helmut.marsiske@science.doe.gov

Overview

Response Deadline
Feb. 22, 2021 Past Due
Posted
Dec. 14, 2020
Open
Dec. 14, 2020
Set Aside
Small Business (SBA)
Place of Performance
Not Provided
Source
Alt Source

Program
SBIR/STTR Phase I
Structure
Grant
Phase Detail
Phase I: Establish the technical merit, feasibility, and commercial potential of the proposed R/R&D efforts and determine the quality of performance of the small business awardee organization.
Duration
6 Months (SBIR) or 1 Year (STTR)
Size Limit
500 Employees
Eligibility Note
Requires partnership between small businesses and nonprofit research institution (only if structured as a STTR)
On 12/14/20 Department of Energy issued SBIR / STTR Topic 36a for Radiation Hard CMOS Sensors and Engineered Substrates for Detectors at High Energy Colliders due 2/22/21.

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