Photonic Integrated Circuit Architectures for Scalable System Objectives (PICASSO)

Background
The Defense Advanced Research Projects Agency (DARPA), through its Microsystems Technology Office (MTO), is soliciting innovative proposals for the Photonic Integrated Circuit Architectures for Scalable System Objectives (PICASSO) program. The goal of this initiative is to explore revolutionary advances in very large-scale photonic circuits, which have the potential to significantly enhance bandwidth, latency, and energy efficiency across various applications including computing, analog signal processing, and sensing.

The solicitation explicitly excludes research that only results in evolutionary improvements to existing technologies. A Controlled Unclassified Information (CUI) Addendum is included to provide key technical details relevant to the program's objectives.

Work Details
Proposals must focus on circuit-level innovations that address two primary technical challenges: preserving optical signal integrity while minimizing excess noise, and ensuring mode control for predictable behavior in photonic circuits.

The program emphasizes the development of circuit-level strategies that can achieve system-level performance gains by maximizing optical processing capabilities while minimizing reliance on electronic transduction. Proposals should include a comprehensive application analysis, system architecture design, and expected performance metrics.

The PICASSO program consists of two technical areas: Technical Area 1 (TA1) involves two phases focusing on circuit-level strategies and generalizability of approaches, while Technical Area 2 (TA2) will leverage TA1 designs for application-specific improvements but is not solicited under this PS. Proposals must deliver functional circuits with documented performance and contribute to a domestically controlled repository for photonic designs.

Period of Performance
The estimated period of performance is expected to start on July 1, 2026.

Place of Performance
The geographic location(s) for performance are not explicitly stated but are expected to utilize domestic photonic foundries and services.