OUSD (R&E) MODERNIZATION PRIORITY: Hypersonics; Microelectronics TECHNOLOGY AREA(S): Materials; Sensors; Electronics; Weapons The technology within this topic is restricted under the International Traffic in Arms Regulation (ITAR), 22 CFR Parts 120-130, which controls the export and import of defense-related material and services, including export of sensitive technical data, or the Export Administration Regulation (EAR), 15 CFR Parts 730-774, which controls dual use items. Offerors must disclose any proposed use of foreign nationals (FNs), their country(ies) of origin, the type of visa or work permit possessed, and the statement of work (SOW) tasks intended for accomplishment by the FN(s) in accordance with the Announcement. Offerors are advised foreign nationals proposed to perform on this topic may be restricted due to the technical data under US Export Control Laws. OBJECTIVE: This topic seeks improved materials, techniques, and processes for integrating high temperature semiconductor dies into packages and higher levels of assembly. The packaged electronics should be robust and reliable enough to operate at 300 C or greater in the very harsh flight environment experienced by a missile defense interceptor. DESCRIPTION: The electronics onboard a missile-defense interceptor must operate in a harsh environment. In particular, these electronics could reach high temperatures due to aero-heating, self-heating, and/or proximity to a propulsion system. High temperatures degrade electrical performance and weaken the ability to withstand mechanical and chemical stresses. Conventional silicon-based electronics fail above a certain temperature. Insulation, isolation, and/or cooling could help protect these electronics, but these protective measures also complicate the interceptor's design and increases its size, weight, and power (SWaP). There are, however, emerging solutions that could extend the upper limit of operating temperature in order to minimize the need for these protective measures. This topic seeks to contribute towards the larger goal of advancing high temperature electronics (HTEs). Numerous advancements are needed in order to further mature HTEs and promote its wider adoption for MDA applications. Of these advancements, this topic specifically focuses on the challenge of packaging HTEs for harsh flight environments. Of particular interest is the ability to attach and connect a high-temperature die to its package. Higher levels of integration are also of interest, but to a lesser extent. There are many complex integration challenges that must be overcome in order to maintain suitable thermal, mechanical, and electrical connections across a wide range of operating temperatures. The exact mission and application is not specified in this topic and is open to suggestion. Examples include remote sensing, control, and actuator electronics located near heat-sources such as rocket engines, divert and attitude control systems, and aero-heated control surfaces. Examples also include power transistors and radiofrequency amplifiers that self-heat and are attached to a rapidly warming heat sink. Other suggestions would be considered but should be relevant to interceptor electronics. For the purposes of this topic, MDA seeks packaged HTEs that can operate at temperatures greater than 300 C. This temperature is assumed to be near the practical upper limit for silicon-on-insulator (SOI) electronics. SOI electronics operating at 300 C or greater would be responsive to this topic. There is a desire to operate at even higher temperatures, using advanced semiconductor materials such as silicon carbide (SiC), if suitable dies and packages are available and affordable enough to support Phase I-III goals. The packaged HTEs might be concurrently exposed to high temperatures, shock (>100 g at lower frequencies and >1000 g at higher frequencies), vibration (>20 g-rms), and acceleration (>50 g). Depending on the application, the HTEs might also be exposed to air, propellant, oxidizer, and/or exhaust gases. They might start at sub-zero pre-launch temperatures, at sea-level, and then rise to high temperatures at near-vacuum pressures as the interceptor rapidly ascends. The HTEs might be exposed to natural and manmade radiation. Mission durations are <30 minutes and the interceptors are not reused afterward. These requirements seem very different than commercial HTE applications and even seem more stressing than space launches. The following questions (among others) should be considered: What is the current state of the practice for HTE and associated packaging? How is the proposed approach innovative? What are its advantages and disadvantages compared to competing alternatives? What are its limitations? What are the developmental risks and contingency plans? How would the technology be commercialized in accordance with the Phase III goals? What high-demand applications, if any, have similar requirements? What other Government-funded efforts (to mature HTEs) could this SBIR augment? Please note that the references listed below (in no particular order) were helpful for understanding the challenges of packaging HTEs. They should not be misconstrued as describing a preferred approach, organization, or technology. They should also not be misconstrued as describing the boundaries within which proposed solutions must fall. They may, however, be used as a benchmark to compare your proposed approach against. Please also note that the technical objectives described within this topic are negotiable and may be adjusted based on pre-release feedback. PHASE I: The objectives of Phase I are as follows: (1) Demonstrate the feasibility and benefit of the proposed approach compared to competing approaches. (2) Build a high-fidelity model of the proposed solution and simulate its electrical performance and robustness in the intended environment. (3) Develop a detailed and executable plan for experimentation and process development in Phase II. This includes creating a complete list and schedule of all of the experiments that would be performed during Phase II. It also includes gathering quotes (with lead-times) for all required materials, equipment, and services (to include back-up suppliers). Phase I is anticipated to be mostly labor, although a small amount may go to materials in order to measure basic properties (to inform models), gain early hands-on experience, and/or demonstrate proof-of-concept. No travel to Government facilities would be required during Phase I. PHASE II: The objectives of Phase II are as follows: (1) Execute the plan developed during Phase I. (2) Continue to improve the fidelity of the model and your capabilities to simulate performance and robustness in harsh conditions. (3) Begin developing a workflow for packaging electronics (and screening for workmanship) that could be commercialized in Phase III. The overall approach should be to produce a large number of samples and take a large number of measurements with which to validate model predictions and inform the next steps. Start simple and incrementally add complexity as confidence in the model and processes increases. Likewise, electrical and environmental tests should start as simple measurements and then progress to flight-representative functional testing during exposure to concurrent environments. Near the end of the program, quantify the limits of the technology by testing to failure. Investigate failures and determine causes. The spend rate should start at Phase I levels and increase linearly to a maximum near the end of Phase II. Major equipment purchases should be deferred until needed in order to continue progress. PHASE III DUAL USE APPLICATIONS: The goal of Phase III is to stand-up a sustainable service to package HTEs for missile defense applications, missile defense contractors, and other US-based customers. It is unlikely that the production volumes needed for missile defense would be large enough to sustain this capability after Phase III ends. Therefore, the offeror should consider (and identify) commercial and/or other defense applications that have similar requirements but that require larger volumes. Another possibility might be to down-market the product in order to meet the price point of customers with less stressing requirements. It is preferable that the offeror intends to provide this service themselves rather than selling or licensing the technology to another company. It is also worth noting that the focus of this SBIR is on integration, rather than the dies or packages themselves. Therefore, it would be acceptable (and in some ways preferable) for the offeror to source these items from other (preferably U.S.-based) suppliers. Other arrangements would be considered. The first flight of this technology would likely be as a redundant and nonessential component onboard a test vehicle, as part of that test vehicle's non-tactical instrumentation (i.e. telemetry package). Therefore, low SWaP and low electromagnetic emissions are crucial to avoid interfering with mission-critical systems and for allowing the packaged HTE to be collocated near existing components with which results could be compared against. Other transition pathways are possible and would be considered. REFERENCES: P. Hagler, P. Henson and R. W. Johnson, "Packaging Technology for Electronic Applications in Harsh High-Temperature Environments," in IEEE Transactions on Industrial Electronics, vol. 58, no. 7, pp. 2673-2682, July 2011, doi: 10.1109/TIE.2010.2047832. Liang-Yu Chen, Robert S. Okojie, Philip G. Neudeck, Gary W. Hunter, and Shun-Tien T. Lin, Packaging of High Temperature SiC Based Electronics , Accessed here: https://nepp.nasa.gov/docuploads/4AEA6FF5-2264-449C-AA1532A7EDFC931F/LiangyuChenLinks701Article.pdf. B. Hunt and A. Tooke, "High temperature electronics for harsh environments," 18th European Microelectronics & Packaging Conference, 2011, pp. 1-5. McCluskey, F. Patrick; Podlesak, Thomas; Grzybowski, Richard. (1997) High Temperature Electronics . CRC Press. KEYWORDS: Electronics, high temperature, HTE, packaging, packages, die, attach, integration, silicon-on-insulator, SOI, silicon carbide, SiC, gallium nitride, GaN, wide bandgap, semiconductors
