Large Footprint Silicon Leadless Chip Carrier (LCC)

RT&L FOCUS AREA(S): General Warfighting Requirements (GWR) TECHNOLOGY AREA(S): Electronics;Materials / Processes;Sensors The technology within this topic is restricted under the International Traffic in Arms Regulation (ITAR), 22 CFR Parts 120-130, which controls the export and import of defense-related material and services, including export of sensitive technical data, or the Export Administration Regulation (EAR), 15 CFR Parts 730-774, which controls dual use items. Offerors must disclose any proposed use of foreign nationals (FNs), their country(ies) of origin, the type of visa or work permit possessed, and the statement of work (SOW) tasks intended for accomplishment by the FN(s) in accordance with section 3.5 of the Announcement. Offerors are advised foreign nationals proposed to perform on this topic may be restricted due to the technical data under US Export Control Laws. OBJECTIVE: Develop a large footprint (~2 cm x 2 cm) silicon Leadless Chip Carrier (LCC) that is strategically radiation-hardened for use with Micro-Electromechanical-System (MEMS) sensors. DESCRIPTION: The performance requirements for sensors used in strategic navigation applications continue to be stringent, necessitating continued innovation for sensor packaging technologies. For commercial applications, conventional LCC materials are typically acceptable for most silicon MEMS sensors, but for strategic applications, the stress induced from coefficient of thermal expansion (CTE) creates mismatches between the package and the sensor, which can result in significant performance errors. Additionally, the radiation-hardness required for strategic applications disqualifies many conventional silicon chip packages from being considered. Examples of existing research for LCC for use with MEMS sensors can be found in the referenced articles [Refs 1-5]. A silicon LCC that can meet the stringent performance requirements of strategic instrumentation is likely to bring value to many existing commercial applications, to support packaging of high performance MEMS which can be used across the commercial class use, for example in automotive class accelerometers among many others. PHASE I: Design a manufacturing process using existing capabilities in the market to produce a package with the desired goals of: 1) having 40 or more pins that are isolated from an electrically conductive substrate; 2) accommodating chips that have the approximate dimensions: 17mm x 17mm x 3mm; and 3) incorporating a hermetic seal ring to be used with a silicon cap. Material space is not constrained and unique designs are encouraged. Analyze all aspects of fabrication to assess and justify the feasibility and practicality of the designed approach. If the Phase I Option is exercised, include the initial design specifications and capabilities description to build prototype solutions in Phase II. PHASE II: Based on the Phase I design and execution plan, fabricate and characterize a small lot (up to Qty: 3) of prototype packages. Characterization shall comprise various parameters, including continuity/isolation of the pins, hermeticity of the package, and mechanical surface features (e.g., flatness, parallelism, heights). Deliver the prototypes by the end of Phase II. PHASE III DUAL USE APPLICATIONS: Based on the prototypes developed in Phase II, continuing development must lead to productization of silicon LCCs. While this technology is aimed at military/strategic applications, LCCs are heavily used in numerous other applications. A silicon LCC that can meet the stringent performance requirements of strategic instrumentation is likely to bring value to many existing commercial applications to support packaging of high performance MEMS, which can be used across the commercial class use for example in automotive class accelerometers. REFERENCES: 1. Lee, K. et al., United States Patent: 3D Interconnect Structure Comprising Through-Silicon Vias Combined with Fine Pitch Backside Metal Redistribution Lines Fabricated Using a Dual Dasmascene Type Approach. US 9,530,740 B2. http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=9530740&OS=9530740&RS=9530740. 2. Edelstein, Daniel et al. Silicon Chip Carrier with Conductive Through-Vias and Method for Fabricating Same. US 2006/0027934 A1. https://patents.google.com/patent/US20060027934A1/en. 3. Zhao, Y. Chip-Scale Package for Integrated Circuits. US 2006/0216857 A1. https://www.freepatentsonline.com/y2006/0216857.html. 4. MA, Qing et al. Interposer For Hermetic Sealing of Sensor Chips and For Their Integration with Integrated Circuit Chips. , US 2016/0280539 A1. https://www.freepatentsonline.com/y2016/0280539.html. 5. Hilton, A. and Temple, D. Wafer-Level Vacuum Packaging of Smart Sensors. Sensors, 16(11), 2016, p. 1819. https://pubmed.ncbi.nlm.nih.gov/27809249/.