PROJECTED CMMC LEVEL REQUIREMENT
Level 2 (Self)
TECHNOLOGY AREAS
None
MODERNIZATION PRIORITIES
Directed Energy (DE)
|
Microelectronics
|
Renewable Energy Generation and Storage
KEYWORDS
Semiconductor; Metal-Oxide Semiconductor Field-Effect Transistor; MOSFET; body diode; high voltage; high current; Directed Energy; DE; High Power Radio Frequency; HPRF; High Power Microwave; HPM; Pulse repetition frequency; PRF; Pulse repetition rate; PRR; Radio Frequency; RF; Solid state
OBJECTIVE
Develop state-of-the-art silicon carbide (SiC) Metal-Oxide Semiconductor Field-Effect Transistors (MOSFETs) packaged for improved size, weight, and power (SWaP) for applications where a high-blocking voltage of more than 10 kV, a high pulsed current density of greater than +/- 5 kA (10 kA ideal), and tens of nanoseconds turn-on time, with low-jitter, are needed for integration with high power microwave (HPM) systems.
DESCRIPTION
The DOW needs SWaP-favorable solutions for fast turn-on and low-jitter SiC MOSFETs to generate high current densities from high voltage capacitors. Current methods of high-current/voltage switching from SiC MOSFETS rely on an array created from series and parallel combinations of commercial off the shelf (COTS) devices [Ref 1]. However, these device arrays are limited in the voltage and amplitude they can switch, have complicated gate driving circuits, and can become size limited. To improve current state-of-the-art capability, the DOW has a need for the development of MOSFETs that have a blocking voltage greater than 10 kV for a single wafer, such that a low-side gate driver can be used to turn on the MOSFET, and a high pulsed-current capability. The requirements for a 5 kA peak current (10 kA ideal) may require multiple parallel combinations of MOSFET wafers, and if so, packaging is to be minimized and vertically stacked packaged arrays should be utilized. It is understood that at higher blocking voltages and current densities an additional diode may be necessary to accommodate the desired pulse current [Ref 2]. Minimizing gate charge and gate resistance for an array of MOSFET is important to alleviate driver requirements, such that a turn on time of less than 30 nanoseconds (ns) is achievable with less than 30 V of gate voltage and 10's of amps of gate current.
PHASE I
Develop a conceptual design for a MOSFET solution meeting the requirements in the Description. Include methodology and prototype performance through description and modeling that will demonstrate the proposed concept. Perform a tradespace assessment of size and performance for the proposed solutions.
Phase I Key Parameters:
Voltage blocking from drain to source (V_DS) for a single semiconductor wafer of greater than 10 kV
Low drain to source resistance (R_DS_on) of 50 milli-ohms or less up to 150 degrees Celsius
Pulsed current discharge greater than 1 kA for a period of 500 ns forward (drain to source) and 500 ns reverse (source to drain).
Paralleling of devices is acceptable to reach current densities
External body diode is acceptable for high reverse currents
Pulsed current design is more critical than a continuous current rating
Turn on time less than 50 ns with a driving gate voltage of equal or less than 30 volts
Propose methods to provide a low inductance packaging of less than 20 nH per device for drain, source, gate, and kelvin pin. Total package size anticipated to be less than 6 x 6 x 3 inches
Thermal dissipation through drain is acceptable
Propose methods to minimize partial discharge voltage degradation
Propose methods for component layout showing size density
Propose methods for improved thermal management through packaging with thermal dissipation to switch up to 1 joule of capacitive energy per discharge at a 5 kHz discharge rate for up to 10 seconds
Propose methods for operational lifetime evaluation
Describe degradation from peak operating conditions
Describe methods for electromagnetic interference (EMI) mitigation
PHASE II
Develop and deliver to the government (Quantity 10) optimized MOSFETs for integration with solid-state pulse generator prototypes developed by the government that meet or exceed the key performance requirements listed below. Topic proposals may propose the use of commercial or Federal facilities to satisfy the performance requirements of this topic, provided the performing SBC satisfies the performance thresholds set out in 15 U.S.C. sec. 638 and as implemented in the SBIR/STTR Policy Directive. Deliver a technical data package (TDP) detailing the design and construction of the packaged MOSFET solution as well as a preliminary datasheet on performance. Support integration and testing activities performed by the DOW.
Phase II Key Parameters:
Voltage blocking from drain to source (V_DS) for a single semiconductor wafer of greater than 10 kV, when evaluated in package in air (ideal) or liquid dielectric (threshold)
Pulsed current discharge greater than 5 kA (10 kA ideal) for a period of 500 ns forward (drain to source) and 500 ns reverse (source to drain)
The MOSFET will be evaluated in short circuit conditions in a low-impedance, capacitive, and low-inductive (RLC) circuit
Paralleling of devices is acceptable to reach current densities
External body diode is acceptable and anticipated for high reverse currents
Pulsed current design is more critical than a continuous current rating
Provide a low inductance packaging of less than 10 nH per device for drain, source, gate, and kelvin pin. Total package size anticipated to be less than 3 x 3 x 1 inches
Evaluate the package for partial discharge voltage degradation
Implement methods for EMI mitigation
Turn on time less than 30 ns with a driving gate voltage of equal or less than 30 volts
Low drain to source resistance (R_DS_on) of 10 milli-ohms or less up to 150 degrees Celsius
Packaging with thermal dissipation to switch up to 2 joules of capacitive energy per discharge at a 50 kHz discharge rate for up to 10 seconds
Implement methods for operation lifetime evaluation
PHASE III DUAL USE APPLICATIONS
Fast rising edge, high voltage MOSFETs enables the generation of higher power HPM systems. A future looking Phase III award shall deliver a complete refinement of parameters to meet requirements and develop manufacturing methods to reduce production time and cost in a commercialization path. For the delivery of MOSFETs as an enabling technology for solid-state HPM systems in such applications as counter-electronics, ultra-wideband radar, and high-power jammers. Other non-HPM applications include alternative energy (such as solar and wind inverters), power distribution, and automotive and transportation.
REFERENCES
Xiao, Q.; Tan, Y.; Wu, X'; Ren, N. and Sheng, K. "A 10KV/200A SiC MOSFET Module with series-parallel hybrid connection of 1200V/50A dies." 2015 IEEE 27th International Symposium on Power Semiconductor Devices & IC's (ISPSD), Hong Kong, China, 2015, pp. 349-352. doi: 10.1109/ISPSD.2015.7123461
Kumar, A. et al. "Effect of capacitive current on reverse body diode of 10kV SiC MOSFETs and external 10kV SiC JBS diodes." 2017 IEEE 5th Workshop on Wide-Bandgap Power Devices and Applications (WiPDA), Albuquerque, NM, USA, 2017, pp. 208-212. doi: 10.1109/WiPDA.2017.8170548
