High Density Chip Interconnect Technology

c. High Density Chip Interconnect Technology With the large channel counts and fine granularity of high energy physics detectors, there is an ever-increasing need for new technologies for higher-density interconnects. Grant applications are sought for the development of new technologies for reducing cost while increasing the density of interconnection of pixelated sensors to readout electronics by enhancing or replacing solder bump-based technologies. Development of cost-effective technologies to connect arrays of thinned integrated circuits (< 50 microns, with areas of ~2x2 cm^2) to high-resistivity silicon sensors with interconnect pitch of 50 microns or less are of interest. Technologies are sought that can minimize dead regions at device edges and/or enable wafer-to-wafer interconnection, by utilizing 3D integration with through-silicon vias or other methods. Present commercial chip packaging and mounting technologies can, at cryogenic temperatures, put mechanical stress on the silicon die which distort the operation of the circuit. Low cost and robust packaging and / or interconnect solutions that do not introduce such stresses would be of advantage especially in the case of large area circuit boards (> 0.5 m on each edge). Questions Contact: Helmut Marsiske, helmut.marsiske@science.doe.gov