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Development of Versatile Wafer Probe System for High Power Devices

ID: DMEA241-002 • Type: SBIR / STTR Topic • Match:  100%
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Description

OUSD (R&E) CRITICAL TECHNOLOGY AREA(S): Microelectronics The technology within this topic is restricted under the International Traffic in Arms Regulation (ITAR), 22 CFR Parts 120-130, which controls the export and import of defense-related material and services, including export of sensitive technical data, or the Export Administration Regulation (EAR), 15 CFR Parts 730-774, which controls dual use items. Offerors must disclose any proposed use of foreign nationals (FNs), their country(ies) of origin, the type of visa or work permit possessed, and the statement of work (SOW) tasks intended for accomplishment by the FN(s) in accordance with the Announcement. Offerors are advised foreign nationals proposed to perform on this topic may be restricted due to the technical data under US Export Control Laws. OBJECTIVE: Develop wafer probe systems (WPSs) for high voltage (HV) devices, e.g. metal-oxide semiconductor field-effect transistors (MOSFETs), diodes, and insulated-gate bipolar transistors (IGBTs) of wide-band gap (WBG) semiconductors such as silicon carbide (SiC). The system must include a wafer chamber, probes, electronics, environmental controllers, safety systems, and software. The WPS must be able to handle high voltage up to 40 kV with a current of 10 A (500A pulsed) through a wafer chuck and probes and must offer a versatile environment, including a vacuum and a wide range of temperatures. In addition, the WPS should also have the capability to perform accurate and reliable measurements of various electrical parameters. DESCRIPTION: WBG semiconductors such as SiC are the most promising materials to develop high-power devices used in a variety of industries, including automobiles, home appliances, power applications, as well as aerospace and defense [1]. As the power electronics market and needs are growing rapidly, more powerful devices allowing more voltage and current are being developed, and this effort has accompanied the evolution of WPS, including source-meter units (SMUs) [2]. For the HV wafer level tests using WPSs, the moisture around wafers must be suppressed by environmental control to protect devices and to avoid early breakdown due to arcing or a strong electric field. To safely operate at HV, Fluorinert liquid has been introduced [3]. However, the application of liquid for electrical testing limits the ability to incorporate optical and/or thermal testing. Commercial manual wafer probers for high-power devices are available to handle up to 20 kV in air or fluorinated bath [4]. A WPS for HV under vacuum is also available [5]. However, WPSs for > 20 kV under vacuum and a wide-range of temperature are not available because of limited technological maturity. The proposed topic seeks to integrate hardware and software to handle 40 kV/10 A DC (500A pulsed) in a vacuum and a wide range of temperature. The final product must include a vacuum chamber with 6 -8 chuck (including cooling and heating system), probes, vibration isolation table, electrical system, software, and safety system. PHASE I: Conduct a feasibility study and investigate the existing technique of HV WPS. Deliver the proposed design, circuits, simulation results, and parts list of a HV WPS that will be used to build a Phase II prototype. Propose sample types for the breakdown testing at 40 kV. The design must assure a high voltage of 40 kV and a high current of 10 A DC (500A pulsed) to test various characteristics of vertical SiC MOSFETs and diodes. The wafer chuck must be able to handle the high voltage and current. The sample chamber must provide a vacuum environment to minimize arcing and for low-temperature operation. The optical window must transmit a wide range of wavelengths, from ultraviolet (UV) to infrared (IR) . The proposed specifications of WPSs are below: Chamber: Chuck must handle 6" 8 wafers and 40kV/10A (500A pulsed) Semi-automatic or full-automatic system Chuck automatic motion covering whole wafer range Probes may be manual for the semi-automatic system Wafer/chuck temperature: ~77K ~700K Must be able to continuously tune wafer temperature from ~77K to ~700K Must have a heater assembly and liquid nitrogen cooling/transfer capability; proportional integral derivative controller (PID) temperature control Vacuum tight chamber: mechanical and turbo pumps for ~1E-5 Torr Optical window Transmission wavelength: ~0.2um >2 um Must have a blanket option to block the window Microscopy with charge-coupled device (CCD) or complementary metal oxide semiconductor (CMOS) sensor Probes 3 (three) probes with 4 (four) vacuum feedthroughs; 1 (one) additional vacuum feedthrough (blanked) Probe tips/connectors/cables capable of handling 0 40 kV/0 10 A DC (500A pulsed) or more and a temperature of ~77K ~700K Vibration isolation table Electrical system Power supply capable of 0 40 kV Consider reverse bias for diode breakdown testing Capable of characterizing 3rd quadrant Capable of measuring body current across wafers Arcing monitor/detector Software Labview control; measurement control with analytical and mathematical operations In-situ data visualization/plotting; data saving Capable of characterizing current and voltage properties in the 3rd quadrant of HV vertical devices Capable of controlling equipment (power supply, source-meter units, vacuum, temperature) Safety system Interlock; arc monitor; operator safety physical shielding/keep-out/encloser PHASE II: Build, test, and deliver a fully functional HV WPS prototype based on the design developed in Phase I. The prototype WPS will undergo rigorous testing to ensure its functionality and safety. This includes conducting various experiments to evaluate its performance under different conditions and scenarios. The final report will provide comprehensive technical documentation, including detailed drawings, circuit diagrams, part lists, and specifications, to facilitate the manufacturing process and address any challenges that were encountered during development. Once completed, the fully functional prototype WPS will be delivered to DMEA for further evaluation and implementation. Consider Underwriters Laboratories (UL)/International Electrotechnical Commission (IEC) regulation at this stage for future commercialization. UL/IEC regulatory certification ensures that the advanced system meets the necessary safety standards and guidelines, which is vital for its successful commercialization. PHASE III DUAL USE APPLICATIONS: There may be opportunities for further development of this system for use in a specific military or commercial application. The Phase II effort aims to improve the testing capability of HV devices, which have various military applications, such as high-power microwave (HPM) pulse generators, electronic safety and arm devices, ignition safety devices, and flight termination systems. This enhancement will pave the way for Phase III, where a new generation of HV WPSs will be constructed. This advanced system will enable the characterization and testing of 40 kV WBG devices at the wafer-level, benefiting both military and commercial industries in multiple areas. REFERENCES: Krishna Shenai, Future Prospects of Widebandgap (WBG) Semiconductor Power Switching, IEEE Trans. Elec. Dev. 62, 248 (2015) Miguel Hinojosa, et al., Evaluation of high-voltage, high-power 4H-SiC insulated-gate bipolar transistors, 2014 IPMHVC Anant K. Agarwal, et al., 1.1 kV 4H-SiC power UMOSFETs, IEEE Elec. Dev. Lett. 18, 586 (1997) https://signatone.com/high-power-stations/ https://www.lakeshore.com/products/categories/material-characterization-products/cryogenic-probe-stations KEYWORDS: High Voltage, High Power, Wafer Probe System, Characterization, Reliability

Overview

Response Deadline
Feb. 7, 2024 Past Due
Posted
Nov. 29, 2023
Open
Jan. 3, 2024
Set Aside
Small Business (SBA)
Place of Performance
Not Provided
Source
Alt Source

Program
SBIR Phase I / II
Structure
Contract
Phase Detail
Phase I: Establish the technical merit, feasibility, and commercial potential of the proposed R/R&D efforts and determine the quality of performance of the small business awardee organization.
Phase II: Continue the R/R&D efforts initiated in Phase I. Funding is based on the results achieved in Phase I and the scientific and technical merit and commercial potential of the project proposed in Phase II. Typically, only Phase I awardees are eligible for a Phase II award
Duration
6 Months - 1 Year
Size Limit
500 Employees
On 11/29/23 Defense Microelectronics Activity issued SBIR / STTR Topic DMEA241-002 for Development of Versatile Wafer Probe System for High Power Devices due 2/7/24.

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