TECHNICAL POINT OF CONTACT (TPOC)
Mahesh Neupane
PROJECTED CMMC LEVEL REQUIREMENT
Level 1
TECHNOLOGY AREAS
None
MODERNIZATION PRIORITIES
Advanced Materials
|
Microelectronics
|
Quantum Science
KEYWORDS
Sliding ferroelectricity; moir superlattice; van der Waals materials; nonvolatile memory; twistronics; two-dimensional materials; ferroelectric domains; graphene field-effect transistor; transition metal dichalcogenides; low-power memory; high-endurance memory; polar homostructures.
OBJECTIVE
Develop ultrafast, high-endurance, nonvolatile memory technology based on sliding ferroelectricity in polar moir van der Waals homostructures.
DESCRIPTION
Twisted stacks of van der Waals (vdW) crystals can form moir superlattices with polar domains whose dipoles are antiferroelectrically aligned and controllable by applied electric fields [1]. Sliding ferroelectricity arises from nm-scale interlayer sliding in vdW materials, coupling in-plane atomic displacement to out-of-plane polarization switching [2]. This mechanism has been demonstrated in bilayer hexagonal boron nitride and semiconducting transition metal dichalcogenides, where polarization reversal can occur with minimal energy dissipation [3]. Recent Department of War investments through the Multidisciplinary University Research Initiative (MURI) have demonstrated advances in twisted two-dimensional heterostructures into atomically thin twistronic memory cell prototypes with potential advantages in speed, endurance, energy efficiency, and scalability [2, 3]. The advancement and prototype development requires a combined multidisciplinary expertise in the design, fabrication, measurement, and modeling of lattice dynamics in twisted moir van der Waals structures, as well as charge transport and optoelectronics in van der Waals materials. The technical approach should exploit the atomically thin nature, low defect density, and strong in-plane bonding of vdW materials to develop sliding ferroelectric nonvolatile memory devices designed to outperform current memory technologies in speed, endurance, and scalability. Engineered nanoscale polar domains in moir superlattices will serve as nonvolatile memory cells based on local ferroelectricity. To demonstrate the electrical and optical readouts in the designed nonvolatile memory devices, the proposal should leverage the scalability and controllability features of well-established systems, such as Graphene field-effect transistors and transition-metal-dichalcogenide-based field-effect transistors.
PHASE I
Demonstrate the feasibility of optimal moir superlattice design for fast and durable sliding ferroelectric domain reversal, including domain wall pinning strategies and nanostructured polar moir superlattice fabrication. Evaluate and analyze electrical and optical readout schemes using graphene field-effect transistors or transition-metal-dichalcogenide-based devices integrated with moir polar domain structures. Perform quantitative analysis of the switching behavior, retention, readout fidelity, speed, energy efficiency, and endurance indicators under optimal device operating conditions. The success of the project will be evaluated using measurable performance indicators, including switching speed, switching energy, endurance, retention, readout fidelity, device-to-device reproducibility, and scalability beyond single-device demonstrations. During Phase I, these values will be quantified to establish appropriate performance targets for Phases II and III and to enable benchmarking against existing nonvolatile memory technologies.
PHASE II
Develop integrated sliding-ferroelectric memory-device prototypes and array-level architectures for more practical use by focusing on systematic evaluation of memory operation benchmarks including endurance, switching speed, and energy efficiency under realistic operating conditions. Particular attention must be paid to address the atomic-scale configuration of the engineered sliding ferroelectric state and the role of domain-wall pinning for controllability. Address scaling and manufacturability beyond single-device demonstrations, aiming initial demonstration of the wafer-scale patterning of local gates, partitioning of vdW structures into individual memory cells, and device packaging of memory arrays. Finally, establish quantitative comparison against competing nonvolatile memory technologies by evaluating switching energy, achievable integration density, and intrinsic fatigue resistance for long-term device operation.
PHASE III DUAL USE APPLICATIONS
Develop a high-speed memory device with low-power device operation, emphasizing energy-efficient memory for edge computing, high-density embedded memory, and robust architectures for defense-relevant electronics. Identify use cases where atomically thin, rapid, durable and low power switching will provide a demonstrable advantage over existing technology, and will describe approaches to industrial adoption and system level integration. Relatively low-power and moderate-speed operation offered by the developed technology can provide added value to the general purpose edge-computing applications. As performance metrics are established during Phases I and II, broader applications will be evaluated, including high-density embedded memory, neuromorphic and in-memory computing, reconfigurable logic, radiation-tolerant electronics, cryogenic control electronics, and memory components integrated with two-dimensional semiconductor platforms.
REFERENCES
K. Yasuda, X. Wang, K. Watanabe, T. Taniguchi, P. Jarillo-Herrero, Science 372, 1458 1462 (2021).
K. Ko, A. Yuk, R. Engelke, S. Carr, J. Kim, D. Park, H. Heo, H.-M. Kim, S.-G. Kim, H. Kim, T. Taniguchi, K. Watanabe, H. Park, E. Kaxiras, S. M. Yang, P. Kim, and H. Yoo, Nature Materials 22, 992 998 (2023).
K. Yasuda, E. Zalys-Geller, X. Wang, D. Bennett, S. S. Cheema, K. Watanabe, T. Taniguchi, E. Kaxiras, P. Jarillo-Herrero, and R. Ashoori, Science 385, 53 56 (2024).
