OUSD (R&E) CRITICAL TECHNOLOGY AREA(S): Hypersonics;Space Technology;Advanced Materials OBJECTIVE: The objective is to develop materials, devices/subcomponents, and integration processes that will enable a fully functional microprocessor capable of continuous operation at elevated temperatures. Here, elevated means anything above the current limitaiton of Silicon Complementary metal oxide semiconductor (Si CMOS) electronics of roughly 250 degrees Celsius. Ultimately, the goal is to develop materials and components capable of operation above 500 degrees Celsius to be used in Department of the Air Force platforms subject to extreme temperatures during operations. DESCRIPTION: The realization of fully functional microprocessors operating at temperatures above 250 degrees Celsius will require advances in the materials and fabrication processes used for transistors/switches, memory elements, and passives, as well as new approaches to heterogenous integration of these various components. Current solutions to thermally protect electronics negatively effect the size, weight, and performance (SWAP) of the systems. Electronics capable of surviving and operating in the high-temperature realm will improve the SWAP of systems by the removal of insulating materials thus improving numerous system capabilities. The topic is expected to deliver at least two lab-scale testbeds of fully packaged electronics capable of operating at temperatures of at least 400 degrees Celsius (up to 500 degrees Celsius desired) without detrimental loss to functionality. PHASE I: This topic is intended for technology proven ready to move directly into a Phase II. Therefore, a Phase I award is not required. The offeror is required to provide detail and documentation in the Direct to Phase II proposal which demonstrates accomplishment of a Phase I-type effort, including a feasibility study. This includes determining, insofar as possible, the scientific and technical merit and feasibility of ideas appearing to have commercial potential. It must have validated the product-market fit between the proposed solution and a potential AF stakeholder. The offeror should have defined a clear, immediately actionable plan with the proposed solution and the AF customer. The feasibility study should have; -Identified the prime potential Department of the Air Force end user(s) for the non-Defense commercial offering to solve the AF need, i.e., how it has been modified; -Described integration cost and feasibility with current mission-specific products; -Described if/how the demonstration can be used by other DoD or Governmental customers. PHASE II: Eligibility for D2P2 is predicated on the offeror having performed a Phase I-like effort predominantly separate from the SBIR Programs. Under the phase II effort, the offeror shall sufficiently develop the technical approach, product, or process in order to conduct a small number of relevant demonstrations. Identification of manufacturing/production issues and or business model modifications required to further improve product or process relevance to improved sustainment costs, availability, or safety, should be documented. These Phase II awards are intended to provide a path to commercialization, not the final step for the proposed solution. The successful Phase 2 effort will build on emerging high temperature electronics technology such as Silicon Carbine (SiC) transistors, ferroelectric memory elements, correlated electron oxide memory elements, and laminate ceramic circuit boards to demonstrate integrated functionality towards a full high-temperature microprocessor. The contractor will establish a research and development strategy that addresses key technical hurdles in one or more of the following areas. Scalable memory fabrication and integration. There is currently no commercially available memory technology that is able to be manufactured in commercial microelectronics foundries, small enough to provide reasonable data densities, and capable of repeated read/write cycles at temperatures above 250 degrees Celsius. Candidate memory technologies must show the potential to satisfy these requirements. The associated read/write protocols should require voltage and current levels that can reasonably be achieved in an integrated microprocessor on a remote air or space platform. Transistor fabrication and integration. Transistors fabricated from wide band gap (WBG) semiconductor materials are the most promising candidates for high temperature logic, switches, and power amplifiers.The NASA SiC Junction Field Effect Transistor (JFET-R) process results in transistors capable of continuous operation at greater than 800 degrees Celsius. However, the speed, density, and voltage/power requirements of these devices must be improved to meet future Department of the Air Force system demands. Furthermore, integrating SiC transistors with emerging memory technology is uncharted ground, and will require novel device and circuit design approaches. Subcomponent integration. A key technology gap is the integration of high temperature logic with high temperature memory into a circuit architecture that can enable the development of digital algorithms for signal processing, data storage, and system control. This requires circuit design specific to these high temperature subcomponents, and the development of packaging processes that ensure the reliability of both the active and passive components of the circuit. The Phase 2 awardee will build on the current state of the art to advance the Technology Readiness Level in one or more of these technology areas by delivering designs and physical prototypes that demonstrate enhanced performance in one or more of the areas above. The awardee will coordinate with the Department of the Air Force technical point of contact (TPOC) via regular information exchange meetings and technical reports. The final deliverable will consist of one or more prototypes devices with demonstrated continuous operation at elevated temperature. PHASE III DUAL USE APPLICATIONS: The contractor will pursue commercialization of the various technologies developed in Phase II for transitioning expanded mission capability to a broad range of potential government and civilian users and alternate mission applications. Direct access with end users and government customers will be provided with opportunities to receive Phase III awards for providing the government additional research & development, or direct procurement of products and services developed in coordination with the program. REFERENCES: 1. https://doi.org/10.1007/s10854-015-3459-4; https://doi.org/10.1016/j.mseb.2010.10.003; 2. https://doi-org.wrs.idm.oclc.org/10.1109/TPEL.2014.2357836; 3. https://doi.org/10.3390/mi10060406; 4. https://doi-org.wrs.idm.oclc.org/10.1146/annurev-matsci-070317-124435; 5. https://doi-org.wrs.idm.oclc.org/10.1109/TPEL.2022.3148192; 6. https://doi-org.wrs.idm.oclc.org/10.1109/ECTC32862.2020.00051; 7. https://doi.org/10.4071/2380-4491.2021.HiTEC.000118 KEYWORDS: high-temperature electronics; high-temperature memory; nonvolatile memory; Silicon Carbide transistors
