RT&L FOCUS AREA(S): Hypersonics;Microelectronics TECHNOLOGY AREA(S): Battlespace Environments;Electronics;Weapons The technology within this topic is restricted under the International Traffic in Arms Regulation (ITAR), 22 CFR Parts 120-130, which controls the export and import of defense-related material and services, including export of sensitive technical data, or the Export Administration Regulation (EAR), 15 CFR Parts 730-774, which controls dual use items. Offerors must disclose any proposed use of foreign nationals (FNs), their country(ies) of origin, the type of visa or work permit possessed, and the statement of work (SOW) tasks intended for accomplishment by the FN(s) in accordance with section 3.5 of the Announcement. Offerors are advised foreign nationals proposed to perform on this topic may be restricted due to the technical data under US Export Control Laws. OBJECTIVE: Develop a widely applicable supporting optical circuit in micro optics to address the supporting optical circuit building block. DESCRIPTION: The optical circuit should provide single, polarization-maintaining input fiber and output fiber, for integration into a gyro assembly. The input fiber would bring broadband light, typical for Interferometric Fiber-Optic Gyro (IFOG) operation, into the package. The optical circuit should provide dual photo detectors, one for sampling and monitoring the input light source and the other serving as the detector for the returned, interfered light from the IFOG optical coil and phase modulator. The output fiber will be bi-directional. Internal to the package there must be a means of directing the input light out onto the output fiber and directing the light returning through the output fiber onto the photo detector. The final circuit should be capable of surviving shock, vibration, and thermal excursions typical of aircraft or missile flight. While some performance specifications may need to be altered, depending on desired gyro performance, a re-usable architecture, assembly methodology, and supply chain would be of great value. As an initial prototype, the target is a 14-butterfly package, making the integration of readout electronics with the internal photo diodes as simple as soldering down the component. Future packaging options will be investigated in later phases. The outcomes of the proposed work are: 1) Closed, hardened optical circuits with sources and detectors on chip to operate an IFOG optical coil. 2) Defined, documented interfaces between micro-optical and electrical components to facilitate rapid, simplified designs of optical/electronic devices and circuits. The Phase I effort will not require access to classified information. If need be, data of the same level of complexity as secured data will be provided to support Phase I work. The Phase II effort may require secure access, if so SSP will process the DD254 to support the contractor for personnel and facility certification for secure access. Work produced in Phase II may become classified. Note: The prospective contractor(s) must be U.S. owned and operated with no foreign influence as defined by DoD 5220.22-M, National Industrial Security Program Operating Manual, unless acceptable mitigating procedures can and have been implemented and approved by the Defense Counterintelligence Security Agency (DCSA). The selected contractor must be able to acquire and maintain a secret level facility and Personnel Security Clearances, in order to perform on advanced phases of this project as set forth by DCSA and SSP in order to gain access to classified information pertaining to the national defense of the United States and its allies; this will be an inherent requirement. The selected company will be required to safeguard classified material IAW DoD 5220.22-M during the advanced phases of this contract. PHASE I: The Phase I effort will consist of proof-of-concept assembly of micro-optical circuits utilizing photodetectors and light sources for the operation of an IFOG system. A laboratory-scale prototype will be constructed incorporating two photodetectors; a broadband light source, all requisite electrical and optical circuitry, and fiber optic patch cables for exterior connections. The function of the circuit will be demonstrated with a surrogate IFOG. The Phase I Option, if exercised, will include single-board packaging of the optical/electronic circuit, as well as requisite tests to confirm function of the device. The Phase I Option, if exercised, will include the initial design specifications and capabilities description to build a prototype solution in Phase II. PHASE II: The Phase II effort will consist of the construction of a ruggedized single-board optical/electronic circuit. The device will incorporate sufficient insulation, vibration isolation, shock and crush protection, and thermal management to operate in conditions characteristic of aircraft or missile flight. Platform surrogate testing will be utilized to verify performance under these conditions. The device will function as a standalone item, excepting input and output to the IFOG or surrogate system. In addition, its exterior interfaces will be sufficiently universal to allow incorporation of a variety of mounting hardware, computer interfaces, and IFOG devices. The architecture of the system will be well documented to facilitate modification and future development. Prepare a Phase III development plan to transition the technology for Navy use and potential commercial use. It is probable that the work under this effort will be classified under Phase II (see Description section for details). PHASE III DUAL USE APPLICATIONS: Phase III will focus on transitioning the product into the final system (for Navy purposes the hypersonic glide-body). Refinement will be focused on integration of the product. Single-board optical/electronic circuits, particularly those with rugged interfaces, will find use in data processing systems, RF photonic systems, and security and safety control systems in both military and civilian use. Other notable uses include plug and play fiber analysis systems. REFERENCES: 1. Brown, Gair D.; Ingold, Joseph P.; Spence, Scote and Paxton, Jack G. Jr. High Impact Shock Testing of Fiber-Optic Components. Fiber and Integrated Optics, 9:4, 1 February 1991, pp. 381-392. https://www.spiedigitallibrary.org/conference-proceedings-of-spie/1366/0000/High-impact-shock-testing-of-fiber-optic-components/10.1117/12.24710.short. 2. Kyriakis-Bitzaros, Efstathios D.; Haralabidis, Nilow; Lagadas, M.;Georgakilas, Alexandros; Moisiadis, Y. and Halkias, George. "Realistic End-to-End Simulation of the Optoelectronic Links and Comparison With the Electrical Interconnections for System-on-Chip Applications." J. Lightwave Technol., 19.10, 1 October 2001, pp. 1532-1543. https://www.osapublishing.org/jlt/abstract.cfm?uri=jlt-19-10-1532. 3. Biere, M.; Gheorghe, L.; Nicolescu, G.; O'Connor, I. and Wainer, G. "Towards the High-Level Design of Optical Networks-on-Chip. Formalization of Opto-Electrical Interfaces." 14th IEEE International Conference on Electronics, Circuits and Systems, 1 January 2008, pp. 427-430. https://www.researchgate.net/publication/4321257_Towards_the_High-Level_Design_of_Optical_Networks-on-Chip_Formalization_of_Opto-Electrical_Interfaces.
