Co-packaging Digital Readout Integrated Circuits and Photonics for Advanced Infrared Imaging

TECHNICAL POINT OF CONTACT (TPOC)
Alexander Brown
Charles Reyner
PROJECTED CMMC LEVEL REQUIREMENT
Level 1
TECHNOLOGY AREAS
None
MODERNIZATION PRIORITIES
Advanced Infrastructure & Advanced Manufacturing
|
Integrated Sensing and Cyber
|
Microelectronics
KEYWORDS
Read-out Integrated Circuit, Photonics, Cryogenic, Optical Interconnects, Data transmission, Electro-optic Infrared, Event-based sensors.
OBJECTIVE
Model, design, and produce a readout integrated circuit with a photonic digital output for an infrared sensor demonstration in a cryogenic environment.
DESCRIPTION
State of the art infrared digital focal plane arrays (FPAs) can produce >20 Gbps when operated at standard video framerates and in large formats. Designing output drivers for this bitstream in a cryogenic environment is nontrivial. It requires careful balancing of the electrical, mechanical, and thermal constraints of the readout integrated circuit (ROIC). Industry surveys indicate that the current state of practice is limited to just under 3 Gbps per channel and 10 pJ/bit. In a large format FPA, the power consumption for data transfer becomes significant and acts to shorten cryocooler lifetimes. A paradigm shift is required. Photonic integrated circuits (PICs) are viewed as a potential solution to the ROIC output driver issue. PICs can improve the ROIC bandwidth, latency, and energy consumption by a factor of 10 or more compared to standard electronic IO practices. Unfortunately, all demonstrations to date have utilized mostly off-the-shelf ROICs with PIC chiplets on an interposer. While this reduces the thermal load of the electrical wiring, it does very little to change the overall power consumption. A fully monolithic design is needed. Fortunately, several foundries now offer 45-180 nm CMOS/PIC capabilities. The envisioned effort will demonstrate a tri-service ready capability to either completely integrate electronics and photonics on a single silicon wafer, or perform foundry-level integration of both a photonic and an electronic layer before detector hybridization. The primary objective of this effort is to demonstrate high-speed, ultra-low-power optical channel operations within cryogenic environments. The supporting Readout Integrated Circuit (ROIC) design must support high-throughput data generation. To facilitate benchmarking and diagnostic testing, the system should feature independent and configurable electrical and optical outputs. While specialized design hardening for space and high-radiation environments is advantageous to support long-term survivability, it remains an optional parameter.
PHASE I
The goal of Phase I is to explore foundry fabrication options to co-package or vertically integrate prototype digital ROICs with photonic chiplets in Phase II. Feasibility of integration, such as bonding, metallization, planarity, and impurities, are critical in evaluation foundry and bonding services for future demonstration. Phase I shall include initial PIC design and planning for operational stability in a cryogenic environment. Design modifications to existing digital ROIC designs should be provided in detail during Phase I. Expected deliverables from Phase I include comprehensive final report detailing PIC design, planned ROIC fabrication modifications, and system integration plan.
PHASE II
Phase II shall consist of the full design and fabrication (i.e., tape-out) of the ROIC with PIC outputs. Testing at cryogenic temperatures will demonstrate optical data output performance and their compatibility with ROIC. Additional characterization, including radiation testing and thermal cycling, should be explored in Phase II. Expected deliverables from Phase II include comprehensive final report on demonstrated protype, associated system architecture, data transmission efficiency, and technical details of integration.
PHASE III DUAL USE APPLICATIONS
Phase III will consist of transitioning developed prototype and identifying commercial market viability. Performers will coordinate with Infrared Focal Plane Array contractors to standardize design considerations for enhancing impact of this critical technology across government services.
REFERENCES
Bandyopadhyay, Saumil, et al. "Single-chip photonic deep neural network with forward-only training." Nature Photonics 18.12 (2024): 1335-1343
Chansky, Evan, et al. "High-Speed SiGe EAMs at Cryogenic Temperatures." 2022 IEEE Photonics Conference (IPC). IEEE, 2022: Estrella, Steven B., et al. "Cryogenic optical interconnects for infrared sensing applications." 2022 IEEE Research and Applications of Photonics in Defense Conference (RAPID). IEEE, 2022
Helkey, Roger, et al. "High-performance photonic integrated circuits on silicon." IEEE Journal of Selected Topics in Quantum Electronics 25.5 (2019): 1-15
Hoessbacher, Claudia, et al. "System-on-chip photonic integrated circuits in silicon photonics and the role of plasmonics." Optical Fiber Communication Conference. Optica Publishing Group, 2023
C. Roeloffzen et al., "Photonic Integrated Circuits for Space Communications," 2024 Optical Fiber Communications Conference and Exhibition (OFC), San Diego, CA, USA, 2024, pp. 1-3.
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