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CHIPS High-Throughput High-Resolution X-ray Laminography/Tomography System for Advanced Packaged Semiconductor Devices and Substrates   3

ID: 1333ND26QNB030031 • Type: Synopsis Solicitation • Match:  85%
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Description

Posted: Feb. 24, 2026, 3:07 p.m. EST

Amendment 0001:

Amendment changes include the following:

  1. The required response date is extended from February 26, 2026 to March 9, 2026
  2. No Statement of work change
  3. Questions and Answers:

Question1: Is there a cleanroom specification?

NIST Response: No. The instrument will be installed in a general purpose lab in the advanced measurement laboratory facility, but not within a cleanroom.

Question 2: Are you flexible on the footprint (size/dimension)

NIST Response: NIST expects the analytical instrument (source, stages, detectors, and shielded enclosure) to fit within the footprint specified by 10.2. Additional space is available in the lab around the instrument for service access, and for support equipment (including chase space for air compressor/dryer if required, and a work area in the lab for control and analysis PCs).

Question 3: Are the devices in JEDEC Trays?

NIST Response: Typically no. NIST requires significant flexibility to load samples that are within the size envelope described by specification 5. Samples will include full wafers, coupons (partial wafers), individual or groups of packaged devices, as well as atypical sample geometries. To meet requirement 5.1, vendors must include 5 sample carriers that are compatible with the automated loading system. Carriers supporting a JEDEC tray is only one possible way to meet that requirement.

See Combined Synopsis Solicitation_1333ND26QNB030031, Attachment 1 - Statement of Work, and Attachment 2 - Applicable Provisions and Clauses attachments for solicitation details.

Posted: Feb. 12, 2026, 11:42 a.m. EST
Background
The CHIPS Metrology program, part of NIST, aims to develop advanced metrology capabilities for the US semiconductor manufacturing ecosystem. This program collaborates with device manufacturers, tool vendors, and materials suppliers to address critical metrology gaps and spur innovation in microelectronics manufacturing.

The contract seeks to procure a high-throughput, high-resolution X-ray Laminography/Tomography system to support research in advanced packaging and new materials.

Work Details
The contractor is required to deliver one analytical instrument system that meets the following specifications:
- **Contract Line Item Number (CLIN) 0001**: X-ray Laminography/Tomography System
- **Quantity**: 1 Each
- **System Resolution**: Must resolve 1 µm Metal/Non-metal line and space pattern.
- **Scan Speed**: Minimum of 0.5 mm³/min. Higher performance in resolution and speed will be favored.
- **Operating Modes**: The system must operate in XCL mode, with additional value for systems that can also operate in XCT mode.
- **X-ray Source Requirements**: Voltage range between 30kV and 160kV with sub-micrometer spatial resolution capabilities.
- **X-ray Detector**: Minimum of 13 megapixels.
- **Sample Handling**: Automatic loading for samples up to 100 mm x 100 mm x 20 mm, with a cassette holding at least 5 samples. The system should perform measurements without user intervention for these samples.

Place of Performance
The work will be performed at NIST Gaithersburg.

Overview

Agency
National Institute of Standards and Technology (NIST) [DOC]
Response Deadline
March 9, 2026, 11:00 a.m. EDT (original: Feb. 26, 2026, 11:00 a.m. EST) Past Due
Posted
Feb. 12, 2026, 11:42 a.m. EST (updated: Feb. 24, 2026, 3:07 p.m. EST)
Set Aside
None
NAICS
334413 - Semiconductor and Related Device Manufacturing
PSC
6640 - Laboratory Equipment And Supplies
Place of Performance
Gaithersburg, MD 20899 United States
Source
Open
Current SBA Size Standard
1250 Employees
Pricing
Likely Fixed Price
Est. Level of Competition
Low
On 2/12/26 National Institute of Standards and Technology issued Synopsis Solicitation 1333ND26QNB030031 for CHIPS High-Throughput High-Resolution X-ray Laminography/Tomography System for Advanced Packaged Semiconductor Devices and Substrates due 3/9/26. The opportunity was issued full & open with NAICS 334413 and PSC 6640.
Primary Contact
Name
Tracy Retterer   Profile
Email
tracy.retterer@nist.gov
Phone
None

Secondary Contact

Name
Donald Collie   Profile
Email
donald.collie@nist.gov
Phone
None

Documents

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Additional Details

Source Agency Hierarchy
COMMERCE, DEPARTMENT OF > NATIONAL INSTITUTE OF STANDARDS AND TECHNOLOGY > DEPT OF COMMERCE NIST
FPDS Organization Code
1341-000SB
Source Organization Code
100182905
Last Updated
March 24, 2026
Last Updated By
tracy.bisson@nist.gov
Archive Date
March 24, 2026