OUSD (R&E) CRITICAL TECHNOLOGY AREA(S): Trusted AI and Autonomy; Microelectronics The technology within this topic is restricted under the International Traffic in Arms Regulation (ITAR), 22 CFR Parts 120-130, which controls the export and import of defense-related material and services, including export of sensitive technical data, or the Export Administration Regulation (EAR), 15 CFR Parts 730-774, which controls dual use items. Offerors must disclose any proposed use of foreign nationals (FNs), their country(ies) of origin, the type of visa or work permit possessed, and the statement of work (SOW) tasks intended for accomplishment by the FN(s) in accordance with the Announcement. Offerors are advised foreign nationals proposed to perform on this topic may be restricted due to the technical data under US Export Control Laws. OBJECTIVE: to develop an artificial intelligence (AI)-powered tool that performs automated design rule check and verification of physical and logical functionality for a reverse engineered schematic design of a circuit card assembly (CCA). DESCRIPTION: USAF electronic systems and subsystems eventually require maintenance work to ensure the continued functionality of aging avionics weapon systems and test equipment. In many cases, technical data and/or support from the original manufacturers may not exist. To ensure proper maintenance of the equipment in these cases, avionics systems and test equipment need to be reverse engineered. The reverse engineering process includes analyzing, measuring, and testing avionics systems down to the component level to determine component functionality and to identify necessary repair requirements. Circuit card assemblies (CCAs) are commonly reverse engineered in support of maintaining legacy avionics systems. A Circuit Card Assembly (CCA) refers to a functional printed circuit board (PCB) that is populated with microelectronic components. In avionics systems, CCAs play a crucial role in ensuring the proper functionality of various electronic components and systems on an aircraft. In situations where avionics systems need to be reverse engineered, a schematic design may need to be created. The schematic for a CCA is fundamental for understanding the design and maintaining the design's electrical connections. To generate a schematic of a CCA, imagery of the PCB and its internal wiring layers must first be collected. Based on these images, data on the connectivity of the microelectronic components on the board can be captured. A combination of the imagery and the connectivity information are essential to generate an accurate schematic of the CCA. Schematic designs must be validated after generation, which is a labor-intensive process to verify the schematic design in conjunction with the data collected in the CCA reverse engineering process. An automated design rule checker is required to reduce the analysis time of CCA schematic designs with the goal of accelerating the validation process. Beyond reducing the analysis time of schematic designs, a design rule checker would also reduce the potential for feedback loops in earlier stages of the CCA reverse engineering process. Thusly, this topic seeks to develop a robust AI-powered tool capable of performing automated design rule check and verification of physical and logical functionality for a reverse engineered schematic design of CCAs. PHASE I: As this is a Direct-to-Phase-II (D2P2) topic, no Phase I awards will be made as a result of this topic. To qualify for this D2P2 topic, the Air Force expects the applicant(s) to demonstrate feasibility by means of a prior Phase I-type effort that does not constitute work undertaken as part of a prior or ongoing SBIR/STTR funding agreement. For this topic, evaluators are expecting that the submittal firm demonstrate the ability to develop a capability that can ingest design documentation for all parts of a CCA. This model should be integrated as a plugin into customer-defined schematic generation tools to validate feasibility that the model can exist on top of existing (and currently utilized) schematic generation software. PHASE II: Phase II of this effort will aim to advance the AI model that has already been demonstrated as a capability. Phase II will include a data collection effort to identify documentation for CCAs and use optical character recognition (OCR), or other automated extraction methods, to identify and extract relevant CCA component information to train the AI model. Given the variety of components and part types that can exist on a CCA, this data collection will require one hundred thousand samples to appropriately train the AI model. Once the model has been trained, the Design Rule Checker (DRC) should automatically verify both the logical and physical integrity of a created schematic design. The AI model should be extensible to be trained on additional data based on testing and evaluation used in mission environments in later SBIR project phases. Specific rules that must be considered in the verification process include identifying specific violations in terms of the physical and logical integrity of the design. The DRC should stop analyzing the schematic design once 500 violations are identified, and the user should be notified of the list of violations. If that threshold is not met in the DRC review, a final report should be generated noting all identified violations in the design. The DRC should also identify any unconnected copper in a component. The DRC should also report broken planes where a net is not electrically connected with the rest of the plane. Once the DRC has completed its comprehensive review of the schematic design, the DRC should output a final report and highlight specific violations (as defined by the rules) in the schematic design for the user's attention and review. PHASE III DUAL USE APPLICATIONS: If Phase II produces an AI-enabled Design Rule Checker, the vendor will be expected to support the Air Force in transitioning the technology for wider US Government use. At this point in development, the tool should automatically check the physical and logical integrity of schematic designs based on a trained AI model built on top of government-defined schematic tools. Working with the Air Force, the company will integrate the technology into the operationally relevant environment for use on mission projects. If necessary, the AI model will be fine-tuned based on testing/evaluation using mission data in mission environments. The results of the integration and subsequent evaluation/analysis of the deployed tool will inform future requirements and development phases (if applicable). REFERENCES: 1. Sierra Circuits Team. How to Run a Design Rule Check (DRC) for Your PCBs. Sierra Circuits. https://www.protoexpress.com/blog/drc-pcb-manufacturing/ 2. Cadence PCB Solutions. Design Rule Check Demystified. Cadence. https://resources.pcb.cadence.com/blog/design-rule-check-demystified 3. What is Design Rule Checking (DRC)? Synopsys. https://www.synopsys.com/glossary/what-is-design-rule-checking.html KEYWORDS: Schematic validation; schematic generation; printed circuit board; circuit card assembly; reverse engineering
