OUSD (R&E) MODERNIZATION PRIORITY: Artificial Intelligence/Machine Learning TECHNOLOGY AREA(S): Sensors; Electronics; Information Systems; Air Platform The technology within this topic is restricted under the International Traffic in Arms Regulation (ITAR), 22 CFR Parts 120-130, which controls the export and import of defense-related material and services, including export of sensitive technical data, or the Export Administration Regulation (EAR), 15 CFR Parts 730-774, which controls dual use items. Offerors must disclose any proposed use of foreign nationals (FNs), their country(ies) of origin, the type of visa or work permit possessed, and the statement of work (SOW) tasks intended for accomplishment by the FN(s) in accordance with the Announcement. Offerors are advised foreign nationals proposed to perform on this topic may be restricted due to the technical data under US Export Control Laws. Please direct questions to the Air Force SBIR/STTR HelpDesk: usaf.team@afsbirsttr.us. OBJECTIVE: Develop a library of signal processing modules that can integrate into existing frameworks such as CFE. Develop techniques to port from a homogenous X86 architecture to a heterogeneous architecture with best of breed GPP, GPU, and FPGA processing. DESCRIPTION: There are numerous Collaborative Framework Environment (CFE) deployments in both ground and airborne environments. In many of these deployments, the signal environment is continuously changing. Rapid deployment of flexible and reconfigurable signal-processing capabilities to address these changes in complicated signal environments is required to provide timely support to current mission requirements. Software-processing modules that will assist with preparation of the signal environment to identify and mitigate interfering signals and to support detection, identification, and collection of target Signals is of Interest are required. In congested signal environments, performing preprocessing of the environment, filtering of interfering signals and noise, will increase the probability of successfully performing the collection and processing of weak, Low Probability of Intercept (LPI), and Low Probability of Detection (LPD) signals. Software modules will be utilized by machine learning algorithms to adapt to changing signal environments while maintaining mission capabilities. The Collaborative Framework Environment (CFE) is a Cross-Service open system architecture that operates on a number of hardware environments. CFE is a fully containerized application that uses micro-services to provide a customizable and extensible solution for hosting complex RF signal processing applications. CFE uses a common SDR-based DSP architecture including GNU radio, and X-Midas building blocks and includes functionality to support a wide array of ISR capabilities to include SIGINT, machine-to-machine communication signals, and real-time ELINT processing. CFE is designed for rapid integration of third-party capabilities and strives for hardware agnostic capabilities, enabling CFE to run on a variety of hosting hardware. The system currently has a dependency on X-86 architectures and there is a need to deploy signal-processing solutions into embedded processors. Often embedded processors that include ARM, GPU, and FPGA resources are available that can be used to meet mission requirements. Today's signal processing environment requires the most effective use of the hardware that is available to perform signal processing. In order to expedite the deployment of signal processing capabilities, the development of signal environment processing tools and a process to optimize the transition of functionality from X86 architectures to embedded processors and FPGA and GPU resources is required. PHASE I: This is a Direct to Phase 2 (D2P2) topic. Phase 1 like proposals will not be evaluated and will be rejected as nonresponsive. For this D2P2 topic, the Government expects that the small business would have accomplished the following in a Phase I-type effort via some other means (e.g. IRAD, or other funded work). It must have developed a concept for a workable prototype or design to address at a minimum the basic capabilities of the stated objective above. Proposal must show, as appropriate to the proposed effort, a demonstrated technical feasibility or nascent capability to meet the capabilities of the stated objective. Proposal may provide example cases of this new capability on a specific application. The documentation provided must substantiate that the proposer has developed a preliminary understanding of the technology to be applied in their Phase II proposal to meet the objectives of this topic. Documentation should include all relevant information including, but not limited to technical reports, test data, prototype designs/models, and performance goals/results. PHASE II: Develop advanced signal processing modules and demonstrate the transition from a homogenous X86 architecture to a more heterogeneous architecture leveraging best of breed GPP, GPU, and FPGA processing. i. Develop and demonstrate a number of signal processing module containers in CFE. ii. Examine and quantify the impacts and resources to implementations in alternative environments such as ARM architectures that include GPP, GPU (CUDA), and FPGA when available in heterogeneous environments. iii. Develop a resource management module to manage available GPP, GPU, and FPGA heterogeneous hardware. iv. Develop matrix of engineering tradeoffs between architectures for implementers. v. Generate Interface Control Document (ICD) and overview descriptions in parallel with the system. Complete the design of the sensor, demonstrate performance of a prototype system through laboratory testing, and deliver the prototype for subsequent evaluation by the government. PHASE III DUAL USE APPLICATIONS: The Government has an interest in transition of the demonstrated concept to existing CFE implementations and in support of new complex requirements. Additionally, applications of the technology to support commercial communications and signal processing applications are possible. Furthermore, technologies for lightweight, high performance airborne sensors with integrated processing have other commercial mission applications. REFERENCES: Yang Qu, Zhiqiang Wu, Ruolin Zhou, Yan Su, "Hierarchical Mixed Signal Detection and Modulation Classification", Circuits and Systems (MWSCAS) 2020 IEEE 63rd International Midwest Symposium on, pp. 213-216, 2020.; P. Cifuentes, W. L. Myrick, S. Sud, J. S. Goldstein and M. D. Zoltowski, "Reduced rank matrix multistage wiener filter with applications in MMSE joint multiuser detection for DS-CDMA," 2002 IEEE International Conference on Acoustics, Speech, and Signal Processing, 2002, pp. III-2605-III-2608, doi: 10.1109/ICASSP.2002.5745181.; K. Umebayashi, R. Takagi, N. Ioroi, Y. Suzuki and J. J. Lehtom ki, "Duty cycle and noise floor estimation with welch FFT for spectrum usage measurements," 2014 9th International Conference on Cognitive Radio Oriented Wireless Networks and Communications (CROWNCOM), 2014, pp. 73-78, doi: 10.4108/icst.crowncom.2014.255311.; Detecting and Classifying Low Probability of Intercept Radar, 2nd Edition a book by Phillip E. Pace, Artech House, 2009.; KEYWORDS: adaptive filter; signal interference mitigation; signal environment characterization; FPGA; GPU; airborne signal processing; statistical signal processing; low probability of intercept; low probability of detection
