HQ072723C0003

Small Business Innovation Research Program (SBIR) Phase II

Synthesizable Register Transfer Logic (RTL) Assertions

Synthesizable Register Transfer Logic (RTL) Assertions

Verification and validation (V&V) of ICs have become progressively difficult as design complexity, the reuse of third-party intellectual property, and malicious attacks on microelectronics have all increased. Given these challenges, the DoD needs automated, user-friendly post-synthesis verification and validation solutions to assure its critical hardware systems. To address this need, ECI presents its AFIRM solution, which represents an innovative, end-to-end framework for the generation, synthesis, testing, and error analysis/reporting of synthesizable Hardware Description Language (HDL) run-time monitors. The ECI AFIRM solution leverages innovative technologies that allow users to select from a library of assertions that are automatically converted into synthesizable run-time monitors. The ECI AFIRM solution also leverages automated scripts for commercial-off-the shelf (COTS) electronic design automation (EDA) tools for hardware design synthesis and testing, reducing development time and costs. It then reports any design failures captured by the synthesized run-time monitors and identifies signals and registers that can explain the failure so the code can be corrected efficiently. The ECI AFIRM solution will provide a cost-effective set of capabilities to reduce testing time, increased performance robustness and enhance hardware assurance while leveraging state-of-the-art assertion-based verification and COTS EDA tool workflows. This will ensure mission success and warfighter safety and security.

The goal of phase II is to continue the R&D efforts initiated in Phase I. Funding is based on the results achieved in Phase I and the scientific and technical merit and commercial potential of the project proposed in Phase II.

DMEA221-001

23-3F2

22.1

Dr. Praveen Chawla